Chapter 4
Register Descriptions
© National Instruments Corporation
4-67
VME-MXI-2 User Manual
DMA Source Configuration Register (SCRx)
SCR1 VMEbus A24 or A32 Offset: D0C (hex)
SCR2 VMEbus A24 or A32 Offset: E0C (hex)
Attributes:
Read/Write
32, 16, 8-bit accessible
31
30
29
28
27
26
25
24
0
0
0
0
0
0
0
0
23
22
21
20
19
18
17
16
1
1
1
0
0
0
0
0
15
14
13
12
11
10
9
8
0
BLOCKEN
0
0
0
ASCEND
TSIZE[1]
TSIZE[0]
7
6
5
4
3
2
1
0
PORT[1]
PORT[0]
AM[5]
AM[4]
AM[3]
AM[2]
AM[1]
AM[0]
This register is used to configure how the DMA controller will access the source of the
data.
Bit
Mnemonic
Description
31-24
0
Reserved
These bits are reserved. Write each of these bits
with 0 when writing the SCRx. The value these
bits return when read is meaningless.
23-21
1
Reserved
These bits are reserved. They must be initialized
to 111 (binary) for the DMA controller to
operate properly. These bits are cleared on a hard
reset and are not affected by a soft reset.
20-15
0
Reserved
These bits are reserved. Write each of these bits
with 0 when writing the SCRx. The value these
bits return when read is meaningless.
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