Chapter 4
Register Descriptions
© National Instruments Corporation
4-11
VME-MXI-2 User Manual
Extender Logical Address Window Register (VWR0)
VMEbus A16 Offset:
A (hex)
Attributes:
Read/Write
16, 8-bit accessible
15
14
13
12
11
10
9
8
0
LAEN
LADIR
1
1
LASIZE[2]
LASIZE[1]
LASIZE[0]
7
6
5
4
3
2
1
0
LABASE[7]
LABASE[6]
LABASE[5]
LABASE[4]
LABASE[3]
LABASE[2]
LABASE[1]
LABASE[0]
You can use this register to control the mapping of VXIbus configuration space between
the VMEbus and the MXIbus. When programming this register, you do not need to
consider the VXIbus configuration space that the VME-MXI-2 itself requires. This is
because the A16 Base Address Decoder has a higher priority than VWR0 and the
VME-MXI-2 will respond to its configuration accesses from both the VMEbus and the
MXIbus. This register conforms to the VXIbus Mainframe Extender specification.
This register takes on a different form when the CMODE bit in the VME-MXI-2 Control
Register (VMCR) is set. This different form does not comply with the VXIbus
Mainframe Extender specification and the CMODE bit should not be set when using a
VXIbus multiframe Resource Manager. For more information on the CMODE bit, refer
to the VMCR register description.
To accommodate 8-bit masters that write to this register, the window is not enabled until
the lower byte of the register is written. Therefore, 8-bit masters should write the upper
byte first, followed by the lower byte.
Bit
Mnemonic
Description
15
0
Reserved
This bit is reserved and returns 0 when read. This
bit can be written with any value.
14
LAEN
Extender Logical Address Window Enable
Writing a 1 to this bit enables mapping of
VMEbus configuration space through the
Extender Logical Address Window. When this
bit is cleared, no VXIbus configuration accesses
are mapped between the VMEbus and the
MXIbus. This bit is cleared by a hard reset and is
not affected by a soft reset.
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