Chapter 2
Functional Overview
© National Instruments Corporation
2-3
VME-MXI-2 User Manual
• VMEbus System
Controller Functions
When the VME-MXI-2 is installed in the first slot of a VMEbus
mainframe it assumes the System Controller responsibilities defined
in the VMEbus specification. These are the VMEbus 16 MHz system
clock driver, VMEbus arbiter, and VMEbus IACK daisy-chain
driver. All of these functions are disabled when the VME-MXI-2 is
not acting as the VMEbus System Controller. The VME-MXI-2 has
the ability to automatically detect if it is installed in the first slot of a
VMEbus mainframe. The VME-MXI-2 does not provide a power
monitor or serial clock driver.
• DMA Controllers 1
and 2
The VME-MXI-2 has two DMA controllers, which operate
independently of each other. Each DMA controller can be
programmed to move data from any source to any destination. The
source and destination can be located on the VMEbus, MXIbus, or
the VME-MXI-2 module’s onboard DRAM. The DMA controllers
will direct the MXIbus and VMEbus master state machines to initiate
data transfer cycles on their respective bus and can access the
onboard DRAM directly. The DMA controllers allow different cycle
types and even different data widths between the source and
destination during the DMA transfer.
• MXI-2 System
Controller Functions
The VME-MXI-2 has the ability to act as the MXI-2 system
controller. When acting as the system controller, the VME-MXI-2
provides the MXIbus arbiter, priority-selection daisy-chain driver,
and bus timeout unit. The VME-MXI-2 can automatically detect from
the MXI-2 cable if it is the system controller.
• VMEbus Control
Signals Transceivers
These transceivers ensure that the VME-MXI-2 meets the loading,
driving, and timing requirements of the VMEbus specification for the
various control signals.
• VMEbus Master
State Machine
This state machine generates VMEbus master data transfer cycles
when directed to do so by the MXI-2 slave state machine, thus
allowing MXIbus cycles to map to the VMEbus. This state machine
will also generate VMEbus master data transfer cycles when
instructed to do so by one of the DMA controllers. The VME-MXI-2
can generate D64, D32, D16, and D08(EO) single, block, and RMW
cycles on the VMEbus in A32 and A24 space. All data transfers can
also be generated in A16 space with the exception of D64 and block
transfers. Two consecutive MXIbus slave cycles are required to
generate a single D64 data transfer cycle. The VME-MXI-2 will not
generate unaligned VMEbus data transfers.
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