Chapter 4
Register Descriptions
© National Instruments Corporation
4-65
VME-MXI-2 User Manual
DMA Transfer Count Register (TCRx)
TCR1 VMEbus A24 or A32 Offset:D08 (hex)
TCR2 VMEbus A24 or A32 Offset:E08 (hex)
Attributes:
Read/Write
32, 16, 8-bit accessible
31
30
29
28
27
26
25
24
TC[31]
TC[30]
TC[29]
TC[28]
TC[27]
TC[26]
TC[25]
TC[24]
23
22
21
20
19
18
17
16
TC[23]
TC[22]
TC[21]
TC[20]
TC[19]
TC[18]
TC[17]
TC[16]
15
14
13
12
11
10
9
8
TC[15]
TC[14]
TC[13]
TC[12]
TC[11]
TC[10]
TC[9]
TC[8]
7
6
5
4
3
2
1
0
TC[7]
TC[6]
TC[5]
TC[4]
TC[3]
TC[2]
TC[1]
TC[0]
This register stores the number of bytes to be transferred.
Bit
Mnemonic
Description
31-0
TC[31:0]
Transfer Count
The transfer count is the number of bytes to be
transferred from the source to the destination
regardless of the width of the data transfers. The
transfer count should be programmed before the
DMA operation is started. When either the
source or destination is using 64-bit data
transfers, the transfer count programmed must be
divisible by 8. The transfer count is decremented
by 1, 2, 4, or 8—depending on the source data
transfer width—as data is read from the source.
Reading the transfer count will return the number
of bytes remaining to be read from the source.
The transfer count has a limit when the source of
the DMA operation will use synchronous
MXIbus burst transfers. This limit does not apply
when the destination uses synchronous MXIbus
burst transfers. The limit differs depending on
the setting of the MXIbus Transfer Limit
control in the VXIplug&play soft front panel,
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