Appendix F
DMA Programming Examples
VME-MXI-2 User Manual
F-8
© National Instruments Corporation
/***********************************************************
* *
* Operation setup: This section sets up one of the DMA *
* controllers to perform a data transfer from the VMEbus *
* to the MXIbus and starts the operation. This process *
* should be repeated for each DMA operation. You can also *
* perform these steps to the other DMA controller to *
* start another operation without waiting for the first *
* one to complete. *
* *
***********************************************************/
/* The following write sets up the DMA Source Configuration
Register. It indicates that the source is located on the VMEbus
and that 32-bit block transfers with the address modifier code
0x3B will be used to access it. Table F-1, at the end of this
appendix, describes the address modifier codes that can be written
to this register. Remember that if the source is DRAM onboard the
VME-MXI-2, the address modifier code should be written with 0.
This step can be skipped if SCR1 was already written with the same
value from a previous DMA operation. This is useful if you will be
performing several DMA operations where the source device remains
constant. */
write(A24, A SCR1, LONGWORD, 0x00E047BB);
/* The following write sets up the base address at which the data
will be acquired from the source. Remember that if the source is
DRAM onboard the VME-MXI-2, the offset within the module's space
should be written to this register, not the VMEbus address of the
source. To compute this value from the source's VMEbus address,
just subtract the VME-MXI-2 module's A24 or A32 base address. */
write(A24, A SAR1, LONGWORD, 0x00200000);
/* The following write sets up the DMA Destination Configuration
Register. It indicates that the destination is located on the
MXIbus and that 32-bit block transfers with the address modifier
code 0x0B will be used to access it. Synchronous burst transfers
will actually be used since the DMA1MBS bit in the SMCR was set in
the Initialization section of this example. Table F-1, at the end
of this appendix, describes the address modifier codes that can be
written to this register. Remember that if the destination is DRAM
onboard the VME-MXI-2, the address modifier code should be written
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