Chapter 4
Register Descriptions
© National Instruments Corporation
4-61
VME-MXI-2 User Manual
4
FRESET
DMA FIFO Reset
This bit can be written with a 1 to reset the DMA
FIFO. It is necessary to reset the FIFO after an
ABORT operation or if a DMA transfer ends due
to an error condition. It is not necessary to clear
the FRESET bit after writing a 1 to it. The FIFO
is reset by a hard reset and is not affected by a
soft reset.
3
ABORT
Abort DMA Operation
This bit can be written with a 1 to abort the
current DMA operation. When a DMA operation
is aborted, it is possible that some data will have
been read from the source that does not get
written to the destination. The ABORT bit
automatically clears when a new DMA operation
is started. It is not necessary to clear the ABORT
bit after writing a 1 to it.
2
STOP
Stop DMA Operation
This bit can be written with a 1 to stop the
current DMA operation. After the STOP bit is
set, the DMA controller immediately stops
reading data from the source and stops writing
data to the destination as soon as the FIFO is
emptied (unlike an ABORT operation, any data
already read from the source is written to the
destination before the DMA controller stops).
After stopping a DMA operation, the same
operation can be allowed to finish by writing the
START bit with a 1, or a new operation can be
started by reprogramming the DMA registers.
After setting the STOP bit, the DMA registers
should not be reprogrammed until the DONE bit
in the DMA Channel Status Register (CHSRx)
becomes 1. The STOP bit will automatically
clear when the START bit is set. It is not
necessary to clear the STOP bit after writing a 1
to it.
1
0
Reserved
This bit is reserved. Write this bit with 0 when
writing the CHORx. The value this bit returns
when read is meaningless.
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