Chapter 4
Register Descriptions
© National Instruments Corporation
4-73
VME-MXI-2 User Manual
14
BLOCKEN
Block Mode DMA
Write a 1 to this bit to cause the DMA controller
to perform block-mode transfers to the
destination. During block mode, the DMA
controller keeps the AS* signal asserted
throughout a series of write cycles to the
destination. The DMA controller automatically
deasserts and reasserts the AS* signal when it
reaches the appropriate transfer size limit for the
bus on which the destination is located (for
example 256 bytes on the VMEbus). In addition,
if the corresponding DMAxMBS bit is set in the
Shared MXIbus Control Register (SMCR), any
block-mode cycles from the DMA controller to
the MXIbus are performed as a synchronous
burst cycle. When this bit is clear, the DMA
controller performs a series of standard single
write cycles to the destination deasserting the
AS* signal after each cycle. This bit is cleared
by a hard reset and is not affected by a soft reset.
13-11
0
Reserved
These bits are reserved. Write each of these bits
with 0 when writing the DCRx. The value these
bits return when read is meaningless.
10
ASCEND
Ascending Addresses
Write a 1 to this bit to cause the DMA controller
to increment the destination address between
each data transfer of the DMA operation. The
destination address is incremented by 1, 2, 4, or
8—depending on the width of the destination
data transfers—resulting in the DMA controller
accessing locations on the destination in
ascending order. When this bit is clear, the DMA
controller does not increment the destination
address throughout the DMA operation, resulting
in all the data going to the same location on the
destination. This bit is cleared by a hard reset
and is not affected by a soft reset.
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