Chapter 4
Register Descriptions
© National Instruments Corporation
4-27
VME-MXI-2 User Manual
3
SCFG
Self-Configuration Status
After a hard reset, the VME-MXI-2 executes an
initialization sequence called self-configuration.
When this bit returns a 1, self-configuration is in
process and the VME-MXI-2 may not be fully
initialized. When this bit returns a 0, self-
configuration is complete and the VME-MXI-2
is initialized. The PASSED bit in the VXIbus
Status Register (VSR) also does not become set
until self-configuration is complete; this prevents
a VXIbus Resource Manager from attempting to
program the VME-MXI-2 before initialization is
complete.
2
MBERR
MXIbus Bus Error Status
If this bit is set, the VME-MXI-2 terminated the
previous MXIbus transfer by driving the MXIbus
BERR* line. This indicates that the cycle was
terminated because of a bus error or a retry
condition. This bit is cleared by hard and soft
resets and on successful MXIbus accesses.
1
0
Reserved
This bit is reserved and returns 0 when read.
0
PARERR
Parity Error Status
If this bit is set, a MXIbus parity error occurred
on either the address or the data portion of the
last MXIbus transfer. This bit is cleared by hard
and soft resets and on MXIbus transfers without
a parity error.
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