Appendix F
DMA Programming Examples
© National Instruments Corporation
F-9
VME-MXI-2 User Manual
with 0. This step can be skipped if DCR1 was already written with
the same value from a previous DMA operation. This is useful if
you will be performing several DMA operations where the
destination device remains constant. */
write(A24, A DCR1, LONGWORD, 0x00E047CB);
/* The following write sets up the base address at which the data
will be written to the destination. Remember that if the
destination is DRAM onboard the VME-MXI-2, the offset within the
module's space should be written to this register, not the VMEbus
address of the destination. To compute this value from the
destination's VMEbus address, just subtract the VME-MXI-2 module's
A24 or A32 base address. */
write(A24, A DAR1, LONGWORD, 0x40000000);
/* The following write sets up the transfer count for the DMA
operation. Remember that the TCRx is written with the number of
bytes to be transferred, regardless of the data width being used
for the source or destination. In this example 4 KB will be
transferred. Also remember the limits imposed on the transfer
count when performing MXIbus synchronous burst operations
described in the TCRx register description in Chapter 4, Register
Descriptions. */
write(A24, A TCR1, LONGWORD, 0x00001000);
/* The following write sets the START bit in CHOR1. This causes
the DMA controller to actually begin the operation. */
write(A24, A CHOR1, LONGWORD, 0x00000001);
/* The following write enables the DMA interrupt condition from
DMA controller 1. Since this occurs after the Start bit is set in
CHOR1, the DONE bit will be clear and the interrupt will not
assert until the DMA operation completes. */
write(A24, A CHCR1, LONGWORD, 0x80004000);
/************************************************************
* *
* Interrupt service routine: This section demonstrates *
* how an interrupt service routine should handle the DMA *
* interrupt condition. *
* *
***********************************************************/
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