Chapter 4
Register Descriptions
© National Instruments Corporation
4-19
VME-MXI-2 User Manual
VXIbus Interrupt Configuration Register (VICR)
VMEbus A16 Offset:
12 (hex)
Attributes:
Read/Write
16, 8-bit accessible
15
14
13
12
11
10
9
8
0
INTEN[7]
INTEN[6]
INTEN[5]
INTEN[4]
INTEN[3]
INTEN[2]
INTEN[1]
7
6
5
4
3
2
1
0
0
INTDIR[7]
INTDIR[6]
INTDIR[5]
INTDIR[4]
INTDIR[3]
INTDIR[2]
INTDIR[1]
You can use this register to control the routing of the seven VMEbus interrupt lines
between the VMEbus and the MXIbus. Any interrupts that the VME-MXI-2 itself
generates will be driven on the VMEbus and must be routed to the MXIbus through this
register if the handler for the interrupt is located on the MXIbus. Interrupt Acknowledge
cycles are mapped in the opposite direction of the corresponding interrupt, which allows
the handler to transparently reach the interrupter when acknowledging an interrupt. More
than one VME-MXI-2 can route the same interrupt level to the same bus (the VMEbus or
MXIbus). This register conforms to the VXIbus Mainframe Extender specification.
Bit
Mnemonic
Description
15
0
Reserved
This bit is reserved. It returns 0 when read. This
bit can be written with any value.
14-8
INTEN[7:1]
Interrupt Enable
Setting these bits individually enables routing of
the seven VMEbus interrupt lines between the
VMEbus and the MXIbus. Any interrupt line
whose corresponding INTEN[7:1] bit is clear is
not routed. These bits are cleared by a hard reset
and are not affected by a soft reset.
7
0
Reserved
This bit is reserved. It returns 0 when read. This
bit can be written with any value.
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