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Chapter 4

Register Descriptions

VME-MXI-2 User Manual

4-26

© National Instruments Corporation

11

MXSCTO

MXIbus System Controller Timeout Status

If the VME-MXI-2 is the MXIbus System
Controller, this bit is set when the VME-MXI-2
terminates a MXIbus cycle with a BERR due to a
bus timeout. This bit is cleared by hard and soft
resets and when read.

10

INTLCK

Interlocked Status

This bit reflects the state of the INTLCK bit in
the VME-MXI-2 Control Register (VMCR).

9

DSYSFAIL

Drive SYSFAIL* Status

This bit reflects the state of the DSYSFAIL bit in
the VME-MXI-2 Control Register (VMCR).

8

FAIR

MXIbus Fair Status

This bit indicates if the VME-MXI-2 is a fair
MXIbus requester. The VME-MXI-2 is fair if
this bit returns a 1, and not fair if it returns a 0.
Refer to Chapter 6, VXIplug&play for the
VME-MXI-2, or Appendix B, Programmable
Configurations, for information on configuring
the VME-MXI-2 as a fair MXIbus requester.

7

MXISC

MXIbus System Controller Status

This bit returns a 1 if the VME-MXI-2 is the
MXIbus System Controller, or a 0 when the
VME-MXI-2 is not the MXIbus System
Controller.

6-4

0

Reserved

These bits are reserved and return 000 (binary)
when read.

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Summary of Contents for VME-MXI-2

Page 1: ...service in house repair center WE BUY USED EQUIPMENT Sell your excess underutilized and idle used equipment We also offer credit for buy backs and trade ins www artisantg com WeBuyEquipment REMOTE IN...

Page 2: ...r Manual January 1996 Edition Part Number 321071A 01 Copyright 1996 National Instruments Corporation All Rights Reserved Artisan Technology Group Quality Instrumentation Guaranteed 888 88 SOURCE www a...

Page 3: ...8 or 800 328 2203 International Offices Australia 03 9 879 9422 Austria 0662 45 79 90 0 Belgium 02 757 00 20 Canada Ontario 519 622 9310 Canada Qu bec 514 694 8521 Denmark 45 76 26 00 Finland 90 527 2...

Page 4: ...NTIAL DAMAGES EVEN IF ADVISED OF THE POSSIBILITY THEREOF This limitation of the liability of National Instruments will apply regardless of the form of action whether in contract or tort including negl...

Page 5: ...in commercial areas Operation of this equipment in a residential area is likely to cause harmful interference in which case the user will be required to correct the interference at his own expense The...

Page 6: ...MXI 2 Description 1 2 VME MXI 2 Description 1 2 Front Panel Features 1 5 Optional Equipment 1 5 Chapter 2 Functional Overview VME MXI 2 Functional Description 2 1 Chapter 3 VME MXI 2 Configuration an...

Page 7: ...l Register VICTR 4 35 VMEbus Status ID Register VSIDR 4 37 VMEbus Interrupt Acknowledge Register 1 VIAR1 4 38 VMEbus Interrupt Acknowledge Register 2 VIAR2 4 39 VMEbus Interrupt Acknowledge Register 3...

Page 8: ...me RM Operation 5 40 Configuring the Logical Address Window 5 40 Configuring the Logical Address Window Example 5 41 Configuring the A24 and A32 Addressing Windows 5 44 Chapter 6 VXIplug play for the...

Page 9: ...Programmable Configurations Appendix C VME MXI 2 Front Panel Configuration Appendix D Differences and Incompatibilities between the VME MXI and the VME MXI 2 Appendix E Configuring a Two Frame System...

Page 10: ...orksheet 4 for MXIbus 3 of Example VMEbus MXIbus System 5 15 Figure 5 11 Logical Address Map Diagram for Your VMEbus MXIbus System 5 16 Figure 5 12 Worksheet 1 Summary of Your VMEbus MXIbus System 5 1...

Page 11: ...ddress Selection E 3 Tables Table 3 1 VME MXI 2 DRAM Configurations 3 11 Table 4 1 VME MXI 2 VXIbus Configuration Register Map 4 2 Table 4 2 VME MXI 2 VMEbus A24 A32 Register Map 4 46 Table 5 1 Base a...

Page 12: ...he VME MXI 2 Chapter 3 VME MXI 2 Configuration and Installation contains the instructions to configure and install the VME MXI 2 module Chapter 4 Register Descriptions contains detailed information on...

Page 13: ...VME MXI 2 This information may be helpful for users of the VME MXI who are moving to the VME MXI 2 Appendix E Configuring a Two Frame System describes how to configure a system containing two mainfra...

Page 14: ...ries programs subprograms subroutines device names functions variables filenames and extensions and for statements and comments taken from program code bold Bold text in this font denotes the messages...

Page 15: ...VMEbus Extensions for Instrumentation VXIbus ANSI VITA 1 1994 VME64 Multisystem Extension Interface Bus Specification Version 2 0 available from National Instruments Corporation VXI 6 VXIbus Mainframe...

Page 16: ...d generation MXIbus Multisystem eXtension Interface bus A VMEbus mainframe equipped with a VME MXI 2 can be connected to other MXIbus devices such as other VMEbus mainframes MXIbus instruments or MXIb...

Page 17: ...ransfers that surpass previous block data throughput benchmarks The new synchronous MXI block protocol increases MXI 2 throughput to a maximum of 33 MB s between two MXI 2 devices All National Instrum...

Page 18: ...to detect MXIbus cycles that map into the VMEbus system MXIbus devices can operate in parallel at full speed over their local system bus and need to synchronize operation with another device only when...

Page 19: ...bus VMEbus System Controller functions 16 MHz system clock driver Data transfer bus arbiter PRI or RR ARBITER Interrupt acknowledge daisy chain driver VMEbus miscellaneous services VMEbus timeout BTO...

Page 20: ...from the VMEbus MXIbus connector System reset pushbutton Optional Equipment Type M1 MXI 2 Cables Straight point connector to straight point connector available in lengths of 1 2 4 8 or 20 m Type M2 M...

Page 21: ...r that converts VMEbus signals into appropriate MXIbus signals From the perspective of the MXIbus the VME MXI 2 implements a MXIbus interface to communicate with other MXIbus devices From the perspect...

Page 22: ...ty Check and Generation AD 31 0 AM 4 0 CONVERT PAR A24 A32 Base Address Decoder A16 Base Address Decoder A32 Window A24 Window A16 Window LA Window VMEbus Address and Address Modifier Xcvrs A 31 1 AM...

Page 23: ...fferent data widths between the source and destination during the DMA transfer MXI 2 System Controller Functions The VME MXI 2 has the ability to act as the MXI 2 system controller When acting as the...

Page 24: ...r returns a BERR to the VMEbus cycle or stores an error status when a parity error is detected MXI 2 Control Signals Transceivers These transceivers ensure that the VME MXI 2 meets the loading driving...

Page 25: ...es the cycle If a parity error is detected during the data phase of write cycle the MXI 2 slave state machine responds with a BERR on the MXIbus VMEbus Bus Timeout Unit The VME MXI 2 has a VMEbus Bus...

Page 26: ...d alerts the appropriate state machines when one occurs This window behaves as defined in VXI 6 the VXIbus Mainframe Extender Specification A24 Window This address decoder monitors the VMEbus and MXIb...

Page 27: ...irements of the VMEbus specification for the D 31 0 signals VMEbus Interrupt and Utility Signal Transceivers These transceivers ensure that the VME MXI 2 meets the loading driving and timing requireme...

Page 28: ...d such damage in handling the module touch the antistatic plastic package to a metal part of your VME chassis before removing the VME MXI 2 from the package Configure the VME MXI 2 This section descri...

Page 29: ...shows the VME MXI 2 The drawing shows the location and factory default settings of the configuration switches and jumpers on the module 1 2 3 6 5 4 1 S2 3 W2 5 DRAM 2 U21 4 U20 6 DRAM Figure 3 1 VME...

Page 30: ...ex The factory default logical address for the VME MXI 2 is 1 which locates the registers in the range C040 hex to C07F hex You can change the logical address of the VME MXI 2 by changing the setting...

Page 31: ...use by the VME MXI 2 The VME MXI 2 modules use this signal to disable the bus timeout unit s on the other VME MXI 2 modules during VMEbus accesses that map to the MXIbus This is done because the MXIbu...

Page 32: ...on the jumper This is the factory default setting which does not connect the VME MXI 2 to any user defined pin You would use this option only if you are installing a single VME MXI 2 in a chassis Fig...

Page 33: ...the automatic circuitry Use switches 3 and 4 of the four position switch at location U21 to control whether MXIbus termination is automatic Figure 3 4a on Figure 3 4b or off Figure 3 4c The settings...

Page 34: ...7 VME MXI 2 User Manual a Automatic MXIbus Termination Default b Terminate MXIbus On c Do Not Terminate MXIbus Off U21 U21 U21 OFF 1 2 3 4 OFF 1 2 3 4 OFF 1 2 3 4 Figure 3 4 MXIbus Termination Artisa...

Page 35: ...nfigured half instead of the user modified settings This is useful in the event that the user configured half of the EEPROM becomes corrupted in such a way that the VME MXI 2 boots to an unusable stat...

Page 36: ...Boot from Factory Configuration Factory Configuration Protected c Boot from User Configuration Factory Configuration Unprotected OFF 1 2 3 4 OFF 1 2 3 4 OFF 1 2 3 4 OFF 1 2 3 4 d Boot from Factory Co...

Page 37: ...llows you to install up to 64 MB The VME MXI 2 supports DRAM speeds of 80 ns or faster Switch S2 is used to select the size of each SIMM If the SIMMs are 4 M x 32 or larger S2 should be in the OFF set...

Page 38: ...x 32 or 512 K x 36 2 MB ON 512 K x 32 or 512 K x 36 512 K x 32 or 512 K x 36 4 MB ON 1 M x 32 or 1 M x 36 4 MB YES ON 1 M x 32 or 1 M x 36 1 M x 32 or 1 M x 36 8 MB ON 2 M x 32 or 2 M x 36 8 MB YES O...

Page 39: ...open any doors or covers blocking access to the mainframe slots 3 Insert the VME MXI 2 in the slot you have selected by aligning the top and bottom of the board with the card edge guides inside the ma...

Page 40: ...7 shows a VME system containing a VME MXI 2 module residing in Slot 1 of a VMEbus mainframe cabled to a device acting as the MXIbus System Controller Notice that you can expand your system to include...

Page 41: ...n the PASSED state The VME MXI 2 enters the PASSED state shortly after a hard reset and cannot be put into the soft reset state afterwards The PASSED bit in the VXIbus Status Register VSR indicates wh...

Page 42: ...on for information on setting the logical address of the VME MXI 2 For example to access the VDTR VXIbus Device Type Register on a VME MXI 2 configured to be Logical Address 1 the base address would b...

Page 43: ...s VMSR VMCR 20 Read Only Write Only 16 8 bit VME MXI 2 Status VME MXI 2 Control VLR 22 Read Write 16 8 bit VMEbus Lock 24 Reserved VLAR 26 Read Only 16 8 bit VME MXI 2 Logical Address 28 Reserved VIST...

Page 44: ...6 along with the VXIbus Device Type Register VDTR on bits 15 to 0 Hard and soft resets have no effect on this register Bit Mnemonic Description 15 14 DEVCLASS 1 0 Device Class These bits return 01 bin...

Page 45: ...rd and soft resets have no effect on this register Bit Mnemonic Description 15 12 REQMEM 3 0 Required Memory These bits determine the amount of memory space that will be requested by the VME MXI 2 in...

Page 46: ...s 15 to 0 Bit Mnemonic Description 15 A24 A32 ACTIVE A24 A32 Active This bit reflects the state of the A24 A32 ENABLE bit in the VXIbus Control Register VCR A 1 indicates that the local A24 A32 regist...

Page 47: ...e VME MXI 2 is ready to execute all of its functionality This bit is not affected by a soft reset 2 PASSED Passed This bit becomes 1 shortly after a hard reset to indicate that the VME MXI 2 has compl...

Page 48: ...address decoding on the VME MXI 2 When this bit is 0 the VME MXI 2 does not respond to accesses to its onboard A24 A32 resources This bit is cleared on a hard reset and is not affected by a soft rese...

Page 49: ...XIbus Status Register VSR is clear forces the VME MXI 2 into the Soft Reset state The VME MXI 2 cannot be put in the Soft Reset state once the PASSED bit becomes 1 When this bit is 0 the VME MXI 2 is...

Page 50: ...define the A24 or A32 base address at which the VME MXI 2 will locate its registers and memory These bits correspond to VMEbus address lines 23 through 8 when the VME MXI 2 is configured for A24 and...

Page 51: ...when the CMODE bit in the VME MXI 2 Control Register VMCR is set This different form does not comply with the VXIbus Mainframe Extender specification and the CMODE bit should not be set when using a...

Page 52: ...p through the Extender Logical Address Window They specify the number of address lines that are compared to the LABASE 7 0 bits when determining if a VXIbus configuration access is in the mapped range...

Page 53: ...inframe Extender specification and the CMODE bit should not be set when using a VXIbus multiframe Resource Manager For more information on the CMODE bit refer to the VMCR register description When acc...

Page 54: ...e Extender A16 Window They specify the number of address lines that are compared to the A16BASE 7 0 bits when determining if a VMEbus A16 access is in the mapped range The A16SIZE 2 0 most significant...

Page 55: ...rent form when the CMODE bit in the VME MXI 2 Control Register VMCR is set This different form does not comply with the VXIbus Mainframe Extender specification and the CMODE bit should not be set when...

Page 56: ...s define the size of the range of A24 addresses that map through the Extender A24 Window They specify the number of address lines that are compared to the A24BASE 7 0 bits when determining if a VMEbus...

Page 57: ...erent form when the CMODE bit in the VME MXI 2 Control Register VMCR is set This different form does not comply with the VXIbus Mainframe Extender specification and the CMODE bit should not be set whe...

Page 58: ...ts define the size of the range of A32 addresses that map through the Extender A32 Window They specify the number of address lines that are compared to the A32BASE 7 0 bits when determining if a VMEbu...

Page 59: ...opposite direction of the corresponding interrupt which allows the handler to transparently reach the interrupter when acknowledging an interrupt More than one VME MXI 2 can route the same interrupt l...

Page 60: ...ing INTEN 7 1 bit is set these bits control the direction that the interrupt is routed The interrupt is routed from the VMEbus to the MXIbus when its INTDIR 7 1 bit is 0 outward and from the MXIbus to...

Page 61: ...ginating on the MXIbus that the VME MXI 2 must sense should be routed through this register to the VMEbus There are no restrictions on either the number of VME MXI 2 modules routing the utility signal...

Page 62: ...this bit causes the VME MXI 2 to route the SYSFAIL signal from the MXIbus to the VMEbus When this bit is clear SYSFAIL is ignored on the MXIbus This bit is cleared by a hard reset and is not affected...

Page 63: ...MXI 2 to route the SYSRESET signal from the VMEbus to the MXIbus When this bit is clear SYSRESET is ignored on the VMEbus You can route SYSRESET in both directions simultaneously This bit is cleared...

Page 64: ...o specify the precise class of a device when it indicates with the DEVCLASS 1 0 bits in the VXIbus ID Register VIDR that it is an Extended Class device The VME MXI 2 is a Mainframe Extender which is o...

Page 65: ...Control register VMCR 13 1 Reserved This bit is reserved and returns 1 when read 12 POSTERR Write Post Error Status This bit returns 1 when a write posted cycle results in an error This is actually t...

Page 66: ...the DSYSFAIL bit in the VME MXI 2 Control Register VMCR 8 FAIR MXIbus Fair Status This bit indicates if the VME MXI 2 is a fair MXIbus requester The VME MXI 2 is fair if this bit returns a 1 and not f...

Page 67: ...rom attempting to program the VME MXI 2 before initialization is complete 2 MBERR MXIbus Bus Error Status If this bit is set the VME MXI 2 terminated the previous MXIbus transfer by driving the MXIbus...

Page 68: ...1 A24 VWR2 and A32 VWR3 Window Registers If CMODE is cleared a Base Size range comparison is used to determine the range of addresses in the windows as described in the VWRx register descriptions If C...

Page 69: ...he VWRx registers the window is not enabled until the lower byte is written Therefore 8 bit masters should write the upper byte first then the lower byte This bit is cleared by hard and soft resets 13...

Page 70: ...bus When the VME MXI 2 must release the bus that it owns it does not do so until it obtains ownership of the other bus VMEbus or the MXIbus If the VME MXI 2 does not own either bus when this bit is wr...

Page 71: ...us Once the VME MXI 2 wins arbitration it does not give up ownership of the MXIbus until either this bit is cleared or a reset occurs This prevents any other MXIbus masters from using the bus so that...

Page 72: ...1 10 9 8 0 0 0 0 0 0 0 0 7 6 5 4 3 2 1 0 LA 7 LA 6 LA 5 LA 4 LA 3 LA 2 LA 1 LA 0 This register provides the logical address of the VME MXI 2 Bit Mnemonic Description 15 8 0 Reserved These bits are res...

Page 73: ...e state of the LINT 3 1 bits in the VMEbus Interrupt Control Register VICTR 12 AFINT VMEbus ACFAIL Interrupt Status This bit returns 1 when the VME MXI 2 is driving the VMEbus IRQ 7 1 selected by LINT...

Page 74: ...is not asserted high If the AFIE bit in the VMEbus Interrupt Control Register VICTR is set an interrupt is also generated when ACFAIL asserts 7 SFINT VMEbus SYSFAIL Interrupt Status This bit returns 1...

Page 75: ...BKOFF SFINT and AFINT bits of the VMEbus Interrupt Status Register VISTR Each condition can be individually enabled in this register Write a number in the range 1 through 7 to these bits to select the...

Page 76: ...his bit is cleared by a hard reset and is not affected by a soft reset 7 0 Reserved This bit is reserved Write a 0 when writing to this bit 6 0 DIRQ 7 1 Drive VMEbus Interrupt Request 7 1 Writing a 1...

Page 77: ...1 0 S 7 S 6 S 5 S 4 S 3 S 2 S 1 S 0 This register contains the Status ID value which is returned during an interrupt acknowledge cycle for an IRQ 7 1 line that is being driven with the DIRQ 7 1 bits...

Page 78: ...Interrupt Acknowledge IACK cycle for interrupt level 1 when read from the MXIbus and returns the Status ID received from the interrupter It can generate 16 bit or 8 bit IACK cycles Generating an 8 bi...

Page 79: ...I2 6 I2 5 I2 4 I2 3 I2 2 I2 1 I2 0 This register generates a VMEbus Interrupt Acknowledge IACK cycle for interrupt level 2 when read from the MXIbus and returns the Status ID received from the interr...

Page 80: ...Interrupt Acknowledge IACK cycle for interrupt level 3 when read from the MXIbus and returns the Status ID received from the interrupter It can generate 16 bit or 8 bit IACK cycles Generating an 8 bi...

Page 81: ...I4 6 I4 5 I4 4 I4 3 I4 2 I4 1 I4 0 This register generates a VMEbus Interrupt Acknowledge IACK cycle for interrupt level 4 when read from the MXIbus and returns the Status ID received from the interr...

Page 82: ...Interrupt Acknowledge IACK cycle for interrupt level 5 when read from the MXIbus and returns the Status ID received from the interrupter It can generate 16 bit or 8 bit IACK cycles Generating an 8 bi...

Page 83: ...I6 6 I6 5 I6 4 I6 3 I6 2 I6 1 I6 0 This register generates a VMEbus Interrupt Acknowledge IACK cycle for interrupt level 6 when read from the MXIbus and returns the Status ID received from the interr...

Page 84: ...Interrupt Acknowledge IACK cycle for interrupt level 7 when read from the MXIbus and returns the Status ID received from the interrupter It can generate 16 bit or 8 bit IACK cycles Generating an 8 bi...

Page 85: ...e Manager this will be done automatically and you can just read the VIDR and VOR to determine the address space A24 or A32 and base address at which the VME MXI 2 is located See the register descripti...

Page 86: ...n SAR1 D10 Read Write 32 16 8 bit DMA Channel 1 Source Address DCR1 D14 Read Write 32 16 8 bit DMA Channel 1 Destination Configuration DAR1 D18 Read Write 32 16 8 bit DMA Channel 1 Destination Address...

Page 87: ...this bit is set the VME MXI 2 responds to IACK cycles of any size and supplies 8 bits of Status ID information The information supplied for the 8 bit Status ID is selected using the SIDLA bit When th...

Page 88: ...writing the DMAICR The value this bit returns when read is meaningless 11 1 Reserved This bit is reserved It must be initialized to 1 for the DMA interrupt to operate properly This bit is cleared on...

Page 89: ...VL 2 0 DMA Interrupt Level These bits select the VMEbus interrupt level that the DMA interrupt condition will assert Write a 7 to these bits for IRQ7 write a 6 for IRQ6 and so on These bits must be in...

Page 90: ...the CLRDMAIE or CLRDONEIE bit in the DMA Channel Control Register CHCRx and then re enabling the interrupt using this register Bit Mnemonic Description 15 12 0 Reserved These bits are reserved Write...

Page 91: ...Write this bit with a 1 to enable the interrupt or a 0 to disable the interrupt The DMAIEN bit should always be written with a 1 This bit always returns a 0 when read 7 0 0 Reserved These bits are re...

Page 92: ...ter provides the upper 8 bits of the Status ID and the VME MXI 2 module s logical address is placed on the lower 8 bits Bit Mnemonic Description 15 8 0 Reserved These bits are reserved Write each of t...

Page 93: ...bit Status ID these bits provide bits 10 through 8 of the Status ID When SID8 is set 8 bit Status ID and SIDLA is clear in the DMAICR these bits provide bits 2 through 0 of the Status ID These bits r...

Page 94: ...bits with 0 when writing the VMCR2 7 IOCONFIG I O Configuration Space Enable This bit controls accesses to I O configuration space the onboard EEPROM A device requesting access to the I O configurati...

Page 95: ...2 User Manual 6 1 0 Reserved These bits are reserved Write these bits with 0 when writing to the VMCR2 0 1 Reserved This bit is reserved Write this bit with 1 when writing to the VMCR2 Artisan Techno...

Page 96: ...MBS DMA Controller 2 MXIbus Block Select This bit combined with the DMAMB S N bit controls whether block cycles to the MXIbus from DMA Controller 2 are performed as normal MXIbus block cycles or synch...

Page 97: ...s Normal When this bit is written with a 1 any DMAxMBS bit that is also being written with a 1 is set synchronous MXIbus burst cycles When this bit is written with a 0 any DMAxMBS bit that is being wr...

Page 98: ...board EEPROM for this bit 17 0 Reserved This bit is reserved Write this bit with 0 when writing to the SMCR 16 1 Reserved This bit is reserved Write this bit with 1 when writing to the SMCR 15 9 0 Res...

Page 99: ...ppendix B Programmable Configurations for more information on the MXIbus timer On a hard reset these bits are initialized to the value stored in the onboard EEPROM for these bits Time Limit Value hex...

Page 100: ...fter all the other DMA registers have been programmed Bit Mnemonic Description 31 8 0 Reserved These bits are reserved Write each of these bits with 0 when writing the CHORx The value these bits retur...

Page 101: ...bit can be written with a 1 to stop the current DMA operation After the STOP bit is set the DMA controller immediately stops reading data from the source and stops writing data to the destination as...

Page 102: ...can also be set after a DMA operation has been stopped with the STOP bit to allow the operation to complete When restarting a stopped DMA operation the START bit should not be set until the DONE bit...

Page 103: ...t Mnemonic Description 31 SET DMAIE Set DMA Interrupt Enable Writing a 1 to this bit enables the corresponding DMA controller to assert the DMA interrupt Writing a 0 to this bit has no effect This bit...

Page 104: ...isables the corresponding DMA controller from interrupting on the DONE condition in the DMA Channel Status Register CHSRx Writing a 0 to this bit has no effect This bit returns a 0 when read if the co...

Page 105: ...ource to the destination regardless of the width of the data transfers The transfer count should be programmed before the DMA operation is started When either the source or destination is using 64 bit...

Page 106: ...s Transfer Limit control in the soft front panel to something other than Unlimited you must program the transfer count to a multiple of the setting of the Transfer Limit control The only exception is...

Page 107: ...onfigure how the DMA controller will access the source of the data Bit Mnemonic Description 31 24 0 Reserved These bits are reserved Write each of these bits with 0 when writing the SCRx The value the...

Page 108: ...standard single read cycles to the source deasserting the AS signal after each cycle This bit is cleared by a hard reset and is not affected by a soft reset 13 11 0 Reserved These bits are reserved Wr...

Page 109: ...us and 11 binary if the source is on the MXIbus These bits are cleared by a hard reset and are not affected by a soft reset 5 0 AM 5 0 Address Modifiers These bits provide the address modifier code us...

Page 110: ...e bits is modified after each successful data transfer to the source during the DMA operation according to the ASCEND bit in the DMA Source Configuration Register SCRx If the initial value of these bi...

Page 111: ...ation 4 71 VME MXI 2 User Manual of the source To compute this value from the VMEbus address of the source just subtract the VME MXI 2 module s A24 or A32 base address Artisan Technology Group Quality...

Page 112: ...configure how the DMA controller accesses the destination of the data Bit Mnemonic Description 31 24 0 Reserved These bits are reserved Write each of these bits with 0 when writing the DCRx The value...

Page 113: ...single write cycles to the destination deasserting the AS signal after each cycle This bit is cleared by a hard reset and is not affected by a soft reset 13 11 0 Reserved These bits are reserved Write...

Page 114: ...and 11 binary if the destination is on the MXIbus These bits are cleared by a hard reset and are not affected by a soft reset 5 0 AM 5 0 Address Modifiers These bits provide the address modifier code...

Page 115: ...ese bits is modified after each successful data transfer to the destination during the DMA operation according to the ASCEND bit in the DMA Destination Configuration Register DCRx If the initial value...

Page 116: ...ruments Corporation VMEbus address of the destination To compute this value from the VMEbus address of the destination just subtract the VME MXI 2 module s A24 or A32 base address Artisan Technology G...

Page 117: ...turns a 1 it indicates that the corresponding DMA controller is asserting the DMA interrupt 30 26 0 Reserved These bits are reserved The value these bits return when read is meaningless 25 DONE DMA Do...

Page 118: ...DMA Channel Operation Register CHORx was written with a 1 13 0 Reserved This bit is reserved The value this bit returns when read is meaningless 12 STOPS DMA Stopped Status bit When this bit returns...

Page 119: ...erminates the operation and sets the retry limit exceeded status in the SERR 1 0 bits When 11 binary is returned it indicates that a data cycle to the source got a MXIbus parity error 1 0 DERR 1 0 Des...

Page 120: ...5 FCR 4 FCR 3 FCR 2 FCR 1 FCR 0 This register indicates the state of the DMA controller s FIFO buffer Bit Mnemonic Description 31 24 0 Reserved These bits are reserved The value these bits return when...

Page 121: ...r you will have to configure the Extender LA A16 A24 and A32 window registers on all your VME VXI 2 modules yourself to allow address mapping in your VMEbus MXIbus system If this is the case consider...

Page 122: ...nclude the address space used by those devices Planning a VMEbus MXIbus System Logical Address Map The VMEbus MXIbus system integrator is the person who configures all the VMEbus and MXIbus devices an...

Page 123: ...XI 2 MXIbus Interface Root Figure 5 1 VMEbus MXIbus System with Multiframe RM on a PC Level 1 Level 2 MXIbus Device MXIbus Device VMEbus Mainframe VME MXI 2 VME MXI 2 VMEbus Mainframe VME MXI 2 VMEbus...

Page 124: ...address mapping window on a VME MXI 2 interface has Base and Size parameters associated with it when the CMODE bit in the VME MXI 2 Control Register VMCR is cleared The Base bits define the base addr...

Page 125: ...0 Range for 55 7 0 to 1 54 to 55 6 0 to 3 54 to 57 5 0 to 7 50 to 57 4 0 to F 50 to 5F 3 0 to 1F 40 to 5F 2 0 to 3F 40 to 7F 1 0 to 7F 00 to 7F 0 0 to FF 00 to FF Base7 Base6 Base5 Base4 Base3 Base2 B...

Page 126: ...Ibus addresses that map into the VMEbus The High bits define the upper bound address of the window and the Low bits indicate the lower bound address of the window To map a range of addresses from the...

Page 127: ...and returns an error if the static logical address assignments prevent assignment of an entire system logical address map Devices with dynamically configurable logical addresses are assigned logical a...

Page 128: ...VMEbus Mainframe 5 VME MXI 2 VMEbus Mainframe 4 MXIbus 2 MXIbus 3 MXIbus 1 Level 1 Level 2 Figure 5 5 Example VMEbus MXIbus System Table 5 2 Example VMEbus MXIbus System Required Logical Addresses Dev...

Page 129: ...Ebus Mainframe 1 and that frame requires two logical addresses Since the value 2 is already a power of two we entered the number 2 into the table 3 Next fill in the blanks for the number of logical ad...

Page 130: ...l address found at the bottom of Figure 5 9 We placed these numbers in the corresponding spaces in Figure 5 7 6 Add up the total number of logical addresses required for the system at the bottom of Fi...

Page 131: ...al address 0 Starting with the MXIbus link on Level 1 which requires the most logical addresses assign the lowest available address range of the logical address map and continue with the next largest...

Page 132: ...west available range within the allocated address range of MXIbus 1 60 to 61 hex Then assign MXIbus 3 the lowest available range of size 2 62 to 63 hex MXIbus Device A needs four logical addresses and...

Page 133: ...r completing charts on the following pages Total number of logical addresses required by MXIbus Link 1 Range 2 Round total number up to next power of two 1 20 Size 8 0 8 First Level MXIbus Link Fill i...

Page 134: ...ks to this mainframe Number of logical addresses required by additional MXIbus links 0 Total number of logical addresses required by this device 23 Range 40 5F Round total number up to the next power...

Page 135: ...8 Figure 5 9 Worksheet 3 for MXIbus 2 of Example VMEbus MXIbus System MXIbus Link MXIbus 3 Device VMEbus Mainframe 4 Number of logical addresses required by device 1 Range 62 Round total number up to...

Page 136: ...your own VMEbus MXIbus system Follow the procedures used to fill out the worksheets for the example VMEbus MXIbus system F E D C B A 9 8 7 6 5 4 3 2 1 0 FF F0 EF E0 DF D0 CF C0 BF B0 AF A0 9F 90 8F 80...

Page 137: ...following pages Total number of logical addresses required by MXIbus Link Range Round total number up to next power of two Size First Level MXIbus Link Fill in after completing charts on the following...

Page 138: ...rame Number of logical addresses required by additional MXIbus links Total number of logical addresses required by this device Range Round total number up to the next power of two Size Device Number o...

Page 139: ...rame Number of logical addresses required by additional MXIbus links Total number of logical addresses required by this device Range Round total number up to the next power of two Size Device Number o...

Page 140: ...rame Number of logical addresses required by additional MXIbus links Total number of logical addresses required by this device Range Round total number up to the next power of two Size Device Number o...

Page 141: ...to Level 1 of the system or to connect a Level 2 MXIbus link to one of the devices on Level 1 Figure 5 16 presents one of these worksheets filled out for the example VMEbus MXIbus system shown in Figu...

Page 142: ...IN Range OUT Device Device LAs Lower LAs Total LAs Range IN Range OUT Device Device LAs Lower LAs Total LAs Range IN Range OUT Device Device LAs Lower LAs Total LAs Range IN Range OUT Device Device L...

Page 143: ...LAs Range IN Range OUT Device Device LAs Lower LAs Total LAs Range IN Range OUT Device Device LAs Lower LAs Total LAs Range IN Range OUT Device Device LAs Lower LAs Total LAs Range IN Range OUT Device...

Page 144: ...indow is then used for mapping configuration space for VXIbus devices and the A16 mapping window is used for mapping space for VMEbus devices When using Base Size windowing formats the minimum size of...

Page 145: ...e To assist you in configuring the A16 window map on the VME MXI 2 interfaces in your system the following pages include worksheets an address map diagram and an example The following steps are used i...

Page 146: ...ow fill in Figure 5 21 for MXIbus 1 MXIbus 1 requires 512 B for MXIbus Device A and 8 KB for VMEbus Mainframe 3 The sum of these values rounds up to the nearest address break of 16 KB We record this i...

Page 147: ...the mainframe does not require any A16 space To do this we set Base 0 Size 0 and Direction Out 13 The VME MXI 2 in VMEbus Mainframe 3 should be assigned the lowest available 8 KB of space assigned to...

Page 148: ...Mainframe 5 VME MXI 2 VMEbus Mainframe 4 MXIbus 2 MXIbus 3 MXIbus 1 Level 1 Level 2 Figure 5 19 Example VMEbus MXIbus System Diagram Table 5 4 Example VMEbus MXIbus System Required A16 Space Device Am...

Page 149: ...frame 4 VMEbus Mainframe 5 MXIbus Device A F00 E00 D00 C00 B00 A00 900 800 700 600 500 400 300 200 100 000 BFFF B000 AFFF A000 9FFF 9000 8FFF 8000 7FFF 7000 6FFF 6000 5FFF 5000 4FFF 4000 3FFF 3000 2FF...

Page 150: ...KB Round up to next address break 2 KB A16 Window Base 8000 Size 5 Direction Out First Level MXIbus Link Amount of A16 space required for devices connected to this VME MXI 2 Round up to next address b...

Page 151: ...up to next address break Total amount of A16 space required for this window 0 Round up total amount to the next address size break 0 First Level VME MXI 2 A16 Window Base Size Direction Second Level...

Page 152: ...p to next address break 4 KB Total amount of A16 space required for this window 7 KB Round up total amount to the next address size break 8 KB First Level VME MXI 2 A16 Window Base 4000 Size 3 Directi...

Page 153: ...to this device 1 2 0 Round up to next address break Total amount of A16 space required for this window 1 KB Round up total amount to the next address size break 1 KB First Level VME MXI 2 A16 Window...

Page 154: ...system Follow the procedures used to fill out the worksheets for the example VMEbus MXIbus system BFFF B000 AFFF A000 9FFF 9000 8FFF 8000 7FFF 7000 6FFF 6000 5FFF 5000 4FFF 4000 3FFF 3000 2FFF 2000 1...

Page 155: ...ess break A16 Window Base Size Direction First Level MXIbus Link Amount of A16 space required for devices connected to this VME MXI 2 Round up to next address break A16 Window Base Size Direction Firs...

Page 156: ...2 Round up to next address break Total amount of A16 space required for this window Round up total amount to the next address size break First Level VME MXI 2 A16 Window Base Size Direction Second Lev...

Page 157: ...2 Round up to next address break Total amount of A16 space required for this window Round up total amount to the next address size break First Level VME MXI 2 A16 Window Base Size Direction Second Lev...

Page 158: ...2 Round up to next address break Total amount of A16 space required for this window Round up total amount to the next address size break First Level VME MXI 2 A16 Window Base Size Direction Second Lev...

Page 159: ...2 Round up to next address break Total amount of A16 space required for this window Round up total amount to the next address size break First Level VME MXI 2 A16 Window Base Size Direction Second Lev...

Page 160: ...he MXIbus For each logical address it reads the VXIbus ID Register located at offset 0 within the device s configuration space If the read is successful that is no BERR a device is present at that log...

Page 161: ...ss space inward and enables the window b Repeats Step 2 recursively c Sets the extender inward logical address mapping window to cover the range up to but not including the extender with the next high...

Page 162: ...dresses 0 and 1 2 Enables the logical address window of the VME MXI 2 found at logical address 0 for the entire outward mapping range of 0 to FF Scans all logical addresses skipping all previously enc...

Page 163: ...ister Base Size format 8 Sets the logical address window of the VME MXI 2 found in VMEbus Mainframe 3 at logical address 60 to cover the devices in that mainframe 60 to 61 and the ranges required of i...

Page 164: ...that extender the VME MXI 2 in VMEbus Mainframe 6 2 Enables the logical address window of the VME MXI 2 at logical address 1 with an outward range of 2 to 3 by writing the value 4702 hex to the Logica...

Page 165: ...u can easily configure a hybrid VXI VME system The settings that you change using the soft front panel are stored in the user configurable half of the EEPROM on the VME MXI 2 As a result the changes r...

Page 166: ...the VMEbus A24 A32 Registers section of Chapter 4 Register Descriptions If you have more than one mainframe extender you must also initialize any Extender Window registers on extenders between the ho...

Page 167: ...ithout exiting the soft front panel or the Cancel button will exit the panel without saving any changes Changes to an instrument s settings are also saved to its EEPROM when you switch to a different...

Page 168: ...to 16 KB Notice that the smallest valid amount in A32 space is 64 KB Caution If you install DRAM into the VME MXI 2 do not attempt to use the first 4 KB of memory space This 4 KB space maps to the reg...

Page 169: ...al operating mode In normal operating mode non interlocked multiple masters can operate simultaneously in the VMEbus MXIbus system A deadlock occurs when a MXIbus master requests use of a VMEbus resou...

Page 170: ...ters never attempt transfers across the MXIbus so there is no chance for deadlock when a MXIbus master attempts a transfer into the VMEbus mainframe You can configure the VME MXI 2 devices in this mai...

Page 171: ...us Settings System Controller You can use the System Controller control to override the automatic first slot detection circuit on the VME MXI 2 When the control is set to Auto the default setting the...

Page 172: ...ut must be disabled and the MXIbus BTO enabled You should disable the BTO of any other BTO module residing in the mainframe If this is not possible set it to its maximum setting to give the MXIbus cyc...

Page 173: ...of the four VMEbus request levels 0 to 3 to request use of the VME Data Transfer Bus DTB The VME MXI 2 requests use of the DTB whenever an external MXIbus device attempts a transfer that maps into the...

Page 174: ...a retry response back to the VMEbus The VME MXI 2 automatically continues to retry the MXI cycle until it receives either a DTACK or BERR response which it then passes to the VMEbus Notice that the VM...

Page 175: ...of the Bus Timeout control described previously under the VME Bus Settings section The options range from 8 s to 128 ms with a default value of 1 ms After the specified amount of time has elapsed the...

Page 176: ...at the VME MXI 2 has a limit on the number of automatic retries it will perform on any one cycle If the limit is exceeded and the VME MXI 2 receives another retry it will pass a retry back to the MXIb...

Page 177: ...irements and power consumption The knowledge base file is intended to be used with software tools that aid in system design integration and verification The knowledge base file is directly accessible...

Page 178: ...D08 data sizes Slave mode D32 D16 and D08 data sizes Optional MXIbus System Controller Can be a fair MXIbus requester Can lock the MXIbus for indivisible transfers Can terminate the MXIbus MXIbus mast...

Page 179: ...odify write transfers RMW slave VMEbus slave read modify write transfers RETRY master VMEbus master retry support RETRY slave VMEbus slave retry support FSD First slot detector SCON VMEbus System Cont...

Page 180: ...ng operating 0 to 95 noncondensing storage EMI FCC Class A Verified Physical Characteristic Specification Board Dimensions VMEbus double height board 233 36 by 160 mm 9 187 by 6 2999 in Connectors Sin...

Page 181: ...tional Instruments Corporation Electrical DC Current Ratings Source Typical Maximum 5 VDC 2 2 A 3 2 A Performance VME Transfer Rate Peak 33 MB s Sustained 23 MB s Artisan Technology Group Quality Inst...

Page 182: ...ry region defined by the VIDR VDTR VCR and VOR registers It is required that when the Resource Manager executes it allocates A24 or A32 space to the VME MXI 2 before the EEPROM can be accessed If you...

Page 183: ...l The four lines of code labeled with the comment set options here should be repeated for each configuration setting that is being written to the EEPROM xxxxxx represents the address of the EEPROM loc...

Page 184: ...amount of space requested by the VME MXI 2 should match the amount of DRAM installed Set it to 16 KB when no DRAM is installed Caution If you install DRAM into the VME MXI 2 do not attempt to use the...

Page 185: ...e corresponding size Notice that the value you should write for any given size differs depending on whether you are requesting A24 or A32 space Size A24 Value Hex A32 Value Hex 16 KB 9F N A 32 KB 8F N...

Page 186: ...module residing in the mainframe If this is not possible set it to its maximum setting to give the MXIbus cycles as much time as possible to complete The lowest value in the allowable range is 15 s an...

Page 187: ...rs Arbiter Timeout An arbitration timeout feature is available on the VME MXI 2 when it is acting as the VMEbus arbiter This feature applies only to a VME MXI 2 in the first slot This feature is enabl...

Page 188: ...f the VME MXI 2 request signal Fair Request The VME MXI 2 is always a Release On Request requester However you can configure whether the VME MXI 2 acts as either a fair or unfair requester on the VMEb...

Page 189: ...cycle if no slave has responded The BTO circuitry is automatically deactivated when the VME MXI 2 is not acting as the MXIbus System Controller The BTO is also disabled when the current MXIbus cycle...

Page 190: ...the VME MXI 2 write the EEPROM byte at offset 2065 hex from the VME MXI 2 base address The following table gives the value that should be written for the corresponding requester type and parity checki...

Page 191: ...P 8 VXI Module Mainframe to Receiver Interconnection The VME MXI 2 module is National Instruments part number 183105x 01 where x is the hardware revision letter Front Panel Figure C 1 shows the front...

Page 192: ...ME MXI 2 User Manual C 2 National Instruments Corporation RESET MXIbus MXI 2 67 105 70 13 2 76 mm inches VME SYSFAIL Figure C 1 VME MXI 2 Front Panel Layout Artisan Technology Group Quality Instrument...

Page 193: ...B18 A19 B20 B21 B22 B23 B24 B25 B26 B27 B28 B29 B30 B31 B32 B33 B34 B35 B36 C1 C2 C3 C4 C5 C6 C7 C8 C9 C10 C11 C12 C13 C14 C15 C16 C17 C18 C19 C20 C21 C22 C23 C24 C25 C26 C27 C28 C29 C30 C31 C32 C33 C...

Page 194: ...18 GND C18 GND D18 TRG 0 A19 AD 22 B19 AD 5 C19 SYSRESET D19 TRG 1 A20 GND B20 GND C20 GND D20 TRG 1 A21 AD 21 B21 AD 4 C21 SYSFAIL D21 TRG 2 A22 GND B22 GND C22 GND D22 TRG 2 A23 AD 20 B23 AD 3 C23 B...

Page 195: ...f the MXIbus signals Table C 2 MXIbus Signal Characteristics Signal Category Voltage Range Max Current Frequency Range Each single ended signal 0 to 3 4 V 60 mA DC to 10 Mhz Each differential signal D...

Page 196: ...ted to any first generation MXIbus device such as the VME MXI A major benefit of MXI 2 is that it combines the MXIbus functionality with all the functionality of the INTX enhancement for the VME MXI o...

Page 197: ...s System Controller Automatic MXIbus Termination Switches available to override automatic detection VMEbus System Controller Automatic The following table lists the configurable features that are prog...

Page 198: ...E bit in the VXIbus Status Control Register VSR VCR Sysfail Inhibit The VME MXI 2 provides a Sysfail Inhibit bit in the VXIbus Status Control Register VSR VCR to prevent it from asserting the SYSFAIL...

Page 199: ...r VMSR VMCR are not implemented Also the entire MXIbus IRQ Configuration Register offset 24 hex on the VME MXI is not implemented As an alternative all these interrupt conditions can be routed to one...

Page 200: ...Register VMSR is set to the value stored in the EEPROM on a hard reset By default the value is 0 The INTLK bit was unaffected by a hard reset on the VME MXI since it was an onboard switch Soft Reset...

Page 201: ...VME MXI 2 modules to extend from one mainframe to another you need to reconfigure the VME MXI 2 interfaces You can find more information about configuring a multiframe system in Chapter 3 VME MXI 2 C...

Page 202: ...esses in the range of 0 to 7F hex The VME MXI 2 is logical address 1 A16 base address C040 hex which is the default logical address Figure E 2a shows the switch setting for logical address 1 Ensure th...

Page 203: ...installed in the first slot in Frame B but in a different slot in Frame A You could also install both in the first slot of their respective mainframes or both in slots other than the first slot MXIbu...

Page 204: ...he value 6100 hex into each of the Extender window registers VWR0 VWR1 VWR2 and VWR3 on the VME MXI 2 in Frame A and the value 6180 hex into each of the Extender window registers on the VME MXI 2 in F...

Page 205: ...bus The only limitation regarding location of the devices is that MXIbus synchronous burst transfers cannot be used for either the source or destination when both devices are located on the MXIbus The...

Page 206: ...ting 8 bit 16 bit and 32 bit data transfers respectively The DATA parameter is a constant for writes that represents the data to be written and is a program variable for reads that store the data read...

Page 207: ...section sets up one of the DMA controllers to perform a data transfer from the VMEbus to the MXIbus and starts the operation Repeat this process for each DMA operation You can also perform these step...

Page 208: ...the same value from a previous DMA operation This is useful if you will be performing several DMA operations where the destination device remains constant write A24 A24BASE DCR1 LONGWORD 0x00E047CB Th...

Page 209: ...read from CHSR1 when the DONE bit became 1 If the expression is false the DMA operation completed successfully and the data at the destination can now be used If the expression is true the SERR 1 0 an...

Page 210: ...eration The following write causes any block transfer to the MXIbus from either DMA controller to be a synchronous burst transfer by setting both DMAxMBS bits in the SMCR You can modify this write so...

Page 211: ...lowing write is required to initialize the DMAIER This is simply enabling the DMA interrupt condition to be routed to the VMEbus write A24 A24BASE DMAIER BYTE 0x09 The following write sets up the DMAI...

Page 212: ...ing several DMA operations where the source device remains constant write A24 A24BASE SCR1 LONGWORD 0x00E047BB The following write sets up the base address at which the data will be acquired from the...

Page 213: ...on Remember that the TCRx is written with the number of bytes to be transferred regardless of the data width being used for the source or destination In this example 4 KB will be transferred Also reme...

Page 214: ...st section applies if DMA controller 1 interrupted and the second section applies if DMA controller 2 interrupted DMA controller 1 section read A24 A24BASE CHSR1 LONGWORD value The following if statem...

Page 215: ...s re arm the DMA interrupt condition This must be done because it is possible that the other DMA controller is also interrupting Notice that the overall DMA interrupt in CHCR2 for DMA controller 2 is...

Page 216: ...A24 nonprivileged block transfer 3A A24 nonprivileged program access 39 A24 nonprivileged data access 38 A24 nonprivileged 64 bit block transfer 37 Reserved 36 Reserved 35 Reserved 34 Reserved 33 Rese...

Page 217: ...User defined 1B User defined 1A User defined 19 User defined 18 User defined 17 User defined 16 User defined 15 User defined 14 User defined 13 User defined 12 User defined 11 User defined 10 User def...

Page 218: ...ontinued Code Hex Description 0A A32 nonprivileged program access 09 A32 nonprivileged data access 08 A32 nonprivileged 64 bit block transfer 07 Reserved 06 Reserved 05 Reserved 04 Reserved 03 Reserve...

Page 219: ...nals and terminology specific to MXIbus VMEbus VXIbus and register bits Refer also to the Glossary The mnemonic types are abbreviated as follows Abbreviation Meaning B Bit MBS MXIbus Signal MXI MXIbus...

Page 220: ...B Extender A24 Window Size A32BASE 7 0 B Extender A32 Window Base A32DIR B Extender A32 Window Direction A32EN B Extender A32 Window Enable A32SIZE 2 0 B Extender A32 Window Size ABORT B Abort DMA Ope...

Page 221: ...ation Address DAR1 R DMA Channel 1 Destination Address DAR2 R DMA Channel 2 Destination Address DCR1 R DMA Channel 1 Destination Configuration DCR2 R DMA Channel 2 Destination Configuration DERR 1 0 B...

Page 222: ...Channel 2 FIFO Count FRESET B DMA FIFO Reset I I1 15 0 B Level 1 Interrupter Status ID I2 31 0 B Level 2 Interrupter Status ID I3 15 0 B Level 3 Interrupter Status ID I4 31 0 B Level 4 Interrupter St...

Page 223: ...xtender Logical Address Window Enable LASIZE 2 0 B Extender Logical Address Window Size LINT 3 1 B Local Interrupt Level LOCKED B VMEbus or MXIbus Locked M MANID 11 0 B Manufacturer ID MBERR B MXIbus...

Page 224: ...R1 R DMA Channel 1 Source Address SAR2 R DMA Channel 2 Source Address SC 15 0 B Subclass SCFG B Self Configuration Status SCR1 R DMA Channel 1 Source Configuration SCR2 R DMA Channel 2 Source Configur...

Page 225: ...hannel 1 Transfer Count TCR2 R DMA Channel 2 Transfer Count TSIZE 1 0 B Transfer Size U UTIL B Utility Signal Support V VCR R VXIbus Control Register VDTR R VXIbus Device Type Register VERSION 3 0 B V...

Page 226: ...Register VMCR2 R VME MXI 2 Control Register 2 VMSR R VME MXI 2 Status Register VMSR2 R VME MXI 2 Status Register 2 VOR R VXIbus Offset Register VSCR R VXIbus Subclass Register VSIDR R VMEbus Status I...

Page 227: ...Instruments has BBS and FTP sites dedicated for 24 hour support with a collection of files and documents to answer most common customer questions From these sites you can also download the latest ins...

Page 228: ...elow to find the technical support number for your country If there is no National Instruments office in your country contact the source from which you purchased your software to obtain support Teleph...

Page 229: ...ed to this problem include the configuration forms from their user manuals Include additional pages if necessary Name Company Address Fax Phone Computer brand Model Processor Operating system include...

Page 230: ..._________ EEPROM Operation U21 switches 1 and 2 __________________________________________ Onboard DRAM SIMM Size S2 __________________________________________________ DRAM SIMMs Installed ___________...

Page 231: ...e ____________________________________________________________ VMEbus Arbiter Timeout _________________________________________________________ Requested Memory Space _________________________________...

Page 232: ...MEbus Devices in System __________________________________________________ ______________________________________________________________________________ Base I O Address of Other Boards _____________...

Page 233: ...on the completeness clarity and organization of the manual If you find errors in the manual please record the page numbers and describe the errors Thank you for your help Name Title Company Address P...

Page 234: ...giga 109 Symbols degrees ohms percent plus or minus A A amperes A16 space The VME 64 KB short address space In VXI the upper 16 KB of A16 space is allocated for use by VXI devices configuration regis...

Page 235: ...n used by VMEbus masters to indicate the address space in which a data transfer is to take place address space A set of 2n memory locations differentiated from other such sets in VMEbus systems by six...

Page 236: ...or signal This signal is asserted by either a slave device or the BTO unit when an incorrect transfer is made on the Data Transfer Bus DTB binary A numbering system with a base of 2 bit Binary digit T...

Page 237: ...CL system clock that is sourced from Slot 0 of a VXIbus mainframe and distributed to Slots 1 through 12 on P2 It is distributed to each slot as a single source single destination signal with a matched...

Page 238: ...r Bus dynamic configuration A method of automatically assigning logical addresses to VXIbus devices at system startup or other configuration times dynamically configured device A device that has its l...

Page 239: ...e granted use of the bus H hard reset Occurs when the mainframe is powered on and when the VMEbus SYSRESET signal is active A hard reset restores all the registers on the VME MXI 2 to their initial va...

Page 240: ...n interrupt acknowledge cycle interrupt level The relative priority at which a device can interrupt INTX Interrupt and Timing Extension a daughter card option that plugs into the two daughter card con...

Page 241: ...ration A device is in master mode if it is performing a bus cycle which it initiated memory device A VMEbus device that not only has configuration registers but also has memory that is accessible thro...

Page 242: ...responsibility Always the first device in the MXIbus daisy chain N nonprivileged access One of the defined types of VMEbus data transfers indicated by certain address modifier codes Each of the defin...

Page 243: ...r or word according to the logic of the system If a bit should be lost in data transmission its loss can be detected by checking the parity PASSED state The state a VMEbus device enters after its self...

Page 244: ...ycle on the VMEbus ROR Release On Request a type of VMEbus arbitration where the current VMEbus master relinquishes control of the bus only when another bus master requests the VMEbus S s seconds Semi...

Page 245: ...rol Register of the VME MXI 2 is set A soft reset clears signals that are asserted by bits in the configuration registers but does not clear configuration information stored in the configuration regis...

Page 246: ...n its Status register SYSRESET A VMEbus signal that is used by a device to indicate a system reset or power up condition System Controller See MXIbus System Controller VMEbus System Controller system...

Page 247: ...rbitration for data transfers across the backplane Installing such a device into any other slot can damage the device the VXIbus VMEbus backplane or both VXIbus VMEbus Extensions for Instrumentation V...

Page 248: ...ple 5 33 MXIbus 4 A16 address map 5 39 summary of A16 address map 5 35 example 5 30 A16 base address configuring 3 3 to 3 4 decoder 2 5 A16 window 2 6 A16 write posting 6 4 to 6 5 A16BASE 7 0 bits 4 1...

Page 249: ...address decoder 2 5 configuring A16 base address 3 3 to 3 4 two frame system E 2 to E 3 base size configuration format 5 4 to 5 6 base and size combinations figure 5 5 base and size combinations table...

Page 250: ...RERR 4 27 PASSED 4 1 4 7 PORT 1 0 4 69 4 74 POSTERR 4 25 READY 4 7 REQMEM 3 0 4 5 RESET 4 1 4 7 4 9 S 15 0 4 24 4 37 SA 31 0 4 70 to 4 71 SABORT 4 78 SCFG 4 27 SERR 1 0 4 79 SET DMAIE 4 63 SET DONEIE...

Page 251: ...3 customer communication xiv H 1 to H 2 D DA 31 0 bits 4 75 to 4 76 data transceivers MXI 2 2 6 VMEbus 2 7 decoders A16 base address decoder 2 5 A24 A32 base address decoder 2 5 logical address 2 6 D...

Page 252: ...s requester B 7 VMEbus timer limit B 5 VME MXI 2 requested memory space B 3 to B 4 electrical specifications A 4 electronic support H 1 to H 2 electrostatic discharge damage from warning 3 1 e mail su...

Page 253: ...intermodule signaling VME MXI 2 3 4 to 3 5 interrupt and utility signal circuitry 2 7 interrupt and utility signal transceivers MXI 2 2 7 VMEbus 2 7 interrupt incompatibilities between VME MXI and VME...

Page 254: ...sheets 5 21 to 5 23 logical address map diagram for VMEbus MXIbus system 5 16 MXIbus 1 of example VMEbus MXIbus system 5 14 MXIbus 1 of VMEbus MXIbus system 5 18 MXIbus 2 of example VMEbus MXIbus syst...

Page 255: ...scriptions A 1 connecting MXIbus cable 3 13 fair requester B 9 parity checking B 9 System Controller two frame systems E 3 termination 3 6 to 3 7 timer limit B 8 MXIbus configuration options auto retr...

Page 256: ...t 4 22 Shared MXIbus Status Control Register SMSR SMCR 4 56 to 4 59 SID8 bit 4 47 SIDLA bit 4 48 signal transceivers See transceivers slave state machine MXI 2 2 5 VMEbus 2 4 slot detection two frame...

Page 257: ...ltiframe RM on PC figure 5 3 required logical addresses for example VMEbus MXIbus system table 5 8 steps to follow 5 7 to 5 12 worksheets for A16 address map A16 space address map diagram 5 34 MXIbus...

Page 258: ...eout BTO B 5 configuring 6 8 overview 2 5 two frame system E 4 capability codes A 2 control signals transceivers 2 3 interrupt and utility signal transceivers 2 7 master state machine 2 3 slave state...

Page 259: ...it 6 9 VMEbus Status ID Register VSIDR 4 37 VME MXI 2 block diagram 2 2 description 1 2 to 1 3 features 1 3 to 1 4 front panel features 1 5 functional description 2 1 to 2 7 getting started 1 1 interm...

Page 260: ...5 VIAR5 4 42 VMEbus Interrupt Acknowledge Register 6 VIAR6 4 43 VMEbus Interrupt Acknowledge Register 7 VIAR7 4 44 VMEbus Interrupt Control Register VICTR 4 35 to 4 36 VMEbus Interrupt Status Register...

Page 261: ...XI 2 User Manual Index 14 National Instruments Corporation W write posting A16 and A24 A32 6 4 to 6 5 X XFERR bit 4 78 Artisan Technology Group Quality Instrumentation Guaranteed 888 88 SOURCE www art...

Page 262: ...service in house repair center WE BUY USED EQUIPMENT Sell your excess underutilized and idle used equipment We also offer credit for buy backs and trade ins www artisantg com WeBuyEquipment REMOTE IN...

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