Chapter 4
Register Descriptions
© National Instruments Corporation
4-47
VME-MXI-2 User Manual
DMA Interrupt Configuration Register (DMAICR)
VMEbus A24 or A32 Offset:
8 (hex)
Attributes:
Read/Write
16, 8-bit accessible
15
14
13
12
11
10
9
8
SID8
SIDLA
1
0
1
0
0
0
7
6
5
4
3
2
1
0
ISTAT
0
0
0
0
ILVL[2]
ILVL[1]
ILVL[0]
This register controls aspects of the DMA interrupt that are configurable. Although the
two DMA controllers are independent, they share a common interrupt condition.
Bit
Mnemonic
Description
15
SID8
8-bit Status/ID
This bit selects between an 8-bit or 16-bit
Status/ID when the DMA interrupt is
acknowledged. When this bit is set, the
VME-MXI-2 responds to IACK cycles of any
size and supplies 8 bits of Status/ID information.
The information supplied for the 8-bit Status/ID
is selected using the SIDLA bit. When this bit is
clear, the VME-MXI-2 responds to 16-bit or
32-bit IACK cycles and supplies 16 bits of
Status/ID information. The 16 bits of Status/ID
are composed of the contents of the DMA
Interrupt Status/ID Register (DMAISIDR) and
the logical address of the VME-MXI-2. The
DMAISIDR appears on the upper 8 bits and the
logical address appears on the lower 8 bits
during the IACK cycle. When this bit is clear,
the VME-MXI-2 does not respond to 8-bit IACK
cycles. This bit is cleared on a hard reset and is
not affected by a soft reset.
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