Index for Volumes 1, 2, 3 and 4
Index:5
INDEX
External Interrupt Architecture 2:603
INTn Instruction 4:217
INTO Instruction 4:217
invala Instruction 3:146
INVD instructions 4:228
INVLPG Instruction 4:230
IP (Instruction Pointer) 1:27, 1:140
IPI (Inter-processor Interrupt) 2:127
IPSR (Interruption Processor Status Register)
IRET Instruction 4:231
IRETD Instruction 4:231
IRR (External Interrupt Request Registers) 2:125
ISR (Interruption Status Register) 2:36, 2:165,
J
J
JMP Instruction 4:243
JMPE Instruction 1:111, 2:597, 4:249
K
Kernel Register (KR) 1:29
KR (Kernel Register) 1:29
L
LAHF Instruction 4:251
Lamport’s Algorithm 2:530
LAR Instruction 4:252
Large Constants 1:53
LC (Loop Count Register) 1:33
ld Instruction 3:151
ldf Instruction 3:157
ldfp Instruction 3:161
LDMXCSR Instruction 4:516
LDS Instruction 4:255
LEA Instruction 4:258
LEAVE Instruction 4:260
LES Instruction 4:255
lfetch Instruction 3:164
LFS Instruction 4:255
LGDT Instruction 4:264
Summary of Contents for ITANIUM ARCHITECTURE
Page 1: ......
Page 7: ...402 Intel Itanium Architecture Software Developer s Manual Rev 2 3 ...
Page 199: ...4 192 Volume 4 Base IA 32 Instruction Reference FWAIT Wait See entry for WAIT ...
Page 352: ...Volume 4 Base IA 32 Instruction Reference 4 345 ROL ROR Rotate See entry for RCL RCR ROL ROR ...
Page 589: ...4 582 Volume 4 IA 32 SSE Instruction Reference ...
Page 590: ...Index Intel Itanium Architecture Software Developer s Manual Rev 2 3 Index ...
Page 591: ...Index Intel Itanium Architecture Software Developer s Manual Rev 2 3 ...
Page 603: ...INDEX Index 12 Index for Volumes 1 2 3 and 4 ...
Page 604: ......