4:84
Volume 4: Base IA-32 Instruction Reference
CPUID—CPU Identification
(Continued)
BREAK;
EAX = 80000004H:
EAX
Processor Name;
EBX
Processor Name;
ECX
Processor Name;
EDX
Processor Name;
BREAK;
DEFAULT: (* EAX > highest value recognized by CPUID *)
EAX
Reserved, Undefined;
EBX
Reserved, Undefined;
ECX
Reserved, Undefined;
EDX
Reserved, Undefined;
BREAK;
ESAC;
memory_fence();
instruction_serialize();
Flags Affected
None.
Additional Itanium System Environment Exceptions
Itanium Reg Faults NaT Register Consumption Abort.
Exceptions (All Operating Modes)
None.
Intel Architecture Compatibility
The CPUID instruction is not supported in early models of the Intel486 processor or in
any Intel architecture processor earlier than the Intel486 processor. The ID flag in the
EFLAGS register can be used to determine if this instruction is supported. If a procedure
is able to set or clear this flag, the CPUID is supported by the processor running the
procedure.
Summary of Contents for ITANIUM ARCHITECTURE
Page 1: ......
Page 7: ...402 Intel Itanium Architecture Software Developer s Manual Rev 2 3 ...
Page 199: ...4 192 Volume 4 Base IA 32 Instruction Reference FWAIT Wait See entry for WAIT ...
Page 352: ...Volume 4 Base IA 32 Instruction Reference 4 345 ROL ROR Rotate See entry for RCL RCR ROL ROR ...
Page 589: ...4 582 Volume 4 IA 32 SSE Instruction Reference ...
Page 590: ...Index Intel Itanium Architecture Software Developer s Manual Rev 2 3 Index ...
Page 591: ...Index Intel Itanium Architecture Software Developer s Manual Rev 2 3 ...
Page 603: ...INDEX Index 12 Index for Volumes 1 2 3 and 4 ...
Page 604: ......