4:16
Volume 4: Base IA-32 Instruction Reference
• A register name implies the contents of the register. A register name enclosed in
brackets implies the contents of the location whose address is contained in that
register. For example, ES:[DI] indicates the contents of the location whose ES
segment relative address is in register DI. [SI] indicates the contents of the
address contained in register SI relative to SI’s default segment (DS) or overridden
segment.
• Parentheses around the “E” in a general-purpose register name, such as (E)SI,
indicates that an offset is read from the SI register if the current address-size
attribute is 16 or is read from the ESI register if the address-size attribute is 32.
• Brackets are also used for memory operands, where they mean that the contents of
the memory location is a segment-relative offset. For example, [SRC] indicates that
the contents of the source operand is a segment-relative offset.
• A
B; indicates that the value of B is assigned to A.
• The symbols =,
,
, and
are relational operators used to compare two values,
meaning equal, not equal, greater or equal, less or equal, respectively. A relational
expression such as A = B is TRUE if the value of A is equal to B; otherwise it is
FALSE.
• The expression “<< COUNT” and “>> COUNT” indicates that the destination
operand should be shifted left or right, respectively, by the number of bits indicated
by the count operand.
The following identifiers are used in the algorithmic descriptions:
•
OperandSize and AddressSize
– The OperandSize identifier represents the
operand-size attribute of the instruction, which is either 16 or 32 bits. The
AddressSize identifier represents the address-size attribute, which is either 16 or
32 bits. For example, the following pseudo-code indicates that the operand-size
attribute depends on the form of the CMPS instruction used.
IF instruction = CMPSW
THEN OperandSize
16;
ELSE
IF instruction = CMPSD
THEN OperandSize
32;
FI;
FI;
See “Operand-Size and Address-Size Attributes” in Chapter 3 of the
Intel
Architecture Software Developer’s Manual, Volume 1
, for general guidelines on how
these attributes are determined.
•
StackAddrSize
– Represents the stack address-size attribute associated with the
instruction, which has a value of 16 or 32 bits (see “Address-Size Attribute for
Stack” in Chapter 4 of the
Intel Architecture Software Developer’s Manual, Volume
1
).
•
SRC
– Represents the source operand.
•
DEST
– Represents the destination operand.
The following functions are used in the algorithmic descriptions:
•
ZeroExtend(value)
– Returns a value zero-extended to the operand-size attribute
of the instruction. For example, if the operand-size attribute is 32, zero extending a
byte value of -10 converts the byte from F6H to a doubleword value of 000000F6H.
If the value passed to the ZeroExtend function and the operand-size attribute are
the same size, ZeroExtend returns the value unaltered.
Summary of Contents for ITANIUM ARCHITECTURE
Page 1: ......
Page 7: ...402 Intel Itanium Architecture Software Developer s Manual Rev 2 3 ...
Page 199: ...4 192 Volume 4 Base IA 32 Instruction Reference FWAIT Wait See entry for WAIT ...
Page 352: ...Volume 4 Base IA 32 Instruction Reference 4 345 ROL ROR Rotate See entry for RCL RCR ROL ROR ...
Page 589: ...4 582 Volume 4 IA 32 SSE Instruction Reference ...
Page 590: ...Index Intel Itanium Architecture Software Developer s Manual Rev 2 3 Index ...
Page 591: ...Index Intel Itanium Architecture Software Developer s Manual Rev 2 3 ...
Page 603: ...INDEX Index 12 Index for Volumes 1 2 3 and 4 ...
Page 604: ......