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Volume 4: IA-32 SSE Instruction Reference
UCOMISS: Unordered Scalar Single-FP Compare and Set EFLAGS
Operation:
switch (xmm1[31-0] <> xmm2/m32[31-0]) {
OF,SF,AF = 000;
case UNORDERED: ZF,PF,CF = 111;
case GREATER_THAN: ZF,PF,CF = 000;
case LESS_THAN: ZF,PF,CF = 001;
case EQUAL: ZF,PF,CF = 100;
}
Description:
The UCOMISS instructions compare the two lowest scalar SP FP numbers and sets the
ZF,PF,CF bits in the EFLAGS register as described above. In addition, the OF, SF and AF
bits in the EFLAGS register are zeroed out. The unordered predicate is returned if either
source operand is a NaN (qNaN or sNaN).
FP Exceptions:
None.
Numeric Exceptions:
Invalid (if SNaN operands), Denormal. Integer EFLAGS values will not be updated
in the presence of unmasked numeric exceptions.
Protected Mode Exceptions:
#GP(0) for an illegal memory operand effective address in the CS, DS, ES, FS or GS
segments; #SS(0) for an illegal address in the SS segment; #PF (fault-code) for a page
fault; #UD if CR0.EM = 1; #NM if TS bit in CR0 is set; #AC for unaligned memory
reference. To enable #AC exceptions, three conditions must be true(CR0.AM is set;
EFLAGS.AC is set; current CPL is 3); #XM for an unmasked SSE numeric exception
(CR4.OSXMMEXCPT =1); #UD for an unmasked SSE numeric exception
(CR4.OSXMMEXCPT =0); #UD if CRCR4.OSFXSR(bit 9) = 0; #UD if CPUID.XMM(EDX
bit 25) = 0.
Real Address Mode Exceptions:
Interrupt 13 if any part of the operand would lie outside of the effective address space
from 0 to 0FFFFH;
#UD if CR0.EM = 1; #NM if TS bit in CR0 is set; #XM for an
unmasked SSE numeric exception (CR4.OSXMMEXCPT =1); #UD for an unmasked SSE
numeric exception (CR4.OSXMMEXCPT =0); #UD if CRCR4.OSFXSR(bit 9) = 0; #UD if
CPUID.XMM(EDX bit 25) = 0.
Virtual 8086 Mode Exceptions:
Same exceptions as in Real Address Mode; #AC for unaligned memory reference if the
current privilege level is 3; #PF (fault-code) for a page fault.
Opcode
Instruction
Description
0F,2E,/r
UCOMISS xmm1, xmm2/m32
Compare lower SP FP number in XMM1 register with lower
SP FP number in XMM2/Mem and set the status flags
accordingly.
Summary of Contents for ITANIUM ARCHITECTURE
Page 1: ......
Page 7: ...402 Intel Itanium Architecture Software Developer s Manual Rev 2 3 ...
Page 199: ...4 192 Volume 4 Base IA 32 Instruction Reference FWAIT Wait See entry for WAIT ...
Page 352: ...Volume 4 Base IA 32 Instruction Reference 4 345 ROL ROR Rotate See entry for RCL RCR ROL ROR ...
Page 589: ...4 582 Volume 4 IA 32 SSE Instruction Reference ...
Page 590: ...Index Intel Itanium Architecture Software Developer s Manual Rev 2 3 Index ...
Page 591: ...Index Intel Itanium Architecture Software Developer s Manual Rev 2 3 ...
Page 603: ...INDEX Index 12 Index for Volumes 1 2 3 and 4 ...
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