Volume 4: IA-32 SSE Instruction Reference
4:565
PEXTRW: Extract Word
Operation:
sel = imm8 & 0x3;
mm_temp = (mm >> (sel * 16)) & 0xffff;
r[15-0] = mm_temp[15-0];
r[31-16] = 0x0000;
Description:
The PEXTRW instruction moves the word in MM selected by the two least significant bits
of imm8 to the lower half of a 32-bit integer register.
Numeric Exceptions:
None.
Protected Mode Exceptions:
#GP(0) for an illegal memory operand effective address in the CS, DS, ES, FS or GS
segments; #SS(0) for an illegal address in the SS segment; #PF(fault-code) for a page
fault; #UD if CR0.EM = 1; #NM if TS bit in CR0 is set. #MF if there is a pending FPU
exception.
Real Address Mode Exceptions:
Interrupt 13 if any part of the operand would lie outside of the effective address space
from 0 to 0FFFFH;
#UD if CR0.EM = 1; #NM if TS bit in CR0 is set. #MF if there is a
pending FPU exception.
Virtual 8086 Mode Exceptions:
Same exceptions as in Real Address Mode; #PF(fault-code) for a page fault.
Additional Itanium System Environment Exceptions
Itanium Reg Faults Disabled FP Register Fault if PSR.dfl is 1
Opcode
Instruction
Description
0F,C5, /r, ib
PEXTRW r32, mm, imm8
Extract the word pointed to by imm8 from MM and move it to a
32-bit integer register.
Summary of Contents for ITANIUM ARCHITECTURE
Page 1: ......
Page 7: ...402 Intel Itanium Architecture Software Developer s Manual Rev 2 3 ...
Page 199: ...4 192 Volume 4 Base IA 32 Instruction Reference FWAIT Wait See entry for WAIT ...
Page 352: ...Volume 4 Base IA 32 Instruction Reference 4 345 ROL ROR Rotate See entry for RCL RCR ROL ROR ...
Page 589: ...4 582 Volume 4 IA 32 SSE Instruction Reference ...
Page 590: ...Index Intel Itanium Architecture Software Developer s Manual Rev 2 3 Index ...
Page 591: ...Index Intel Itanium Architecture Software Developer s Manual Rev 2 3 ...
Page 603: ...INDEX Index 12 Index for Volumes 1 2 3 and 4 ...
Page 604: ......