4:258
Volume 4: Base IA-32 Instruction Reference
LEA—Load Effective Address
Description
Computes the effective address of the second operand (the source operand) and stores
it in the first operand (destination operand). The source operand is a memory address
(offset part) specified with one of the processors addressing modes; the destination
operand is a general-purpose register. The address-size and operand-size attributes
affect the action performed by this instruction, as shown in the following table. The
operand-size attribute of the instruction is determined by the chosen register; the
address-size attribute is determined by the attribute of the code segment.
Different assemblers may use different algorithms based on the size attribute and
symbolic reference of the source operand.
Operation
IF OperandSize = 16 AND AddressSize = 16
THEN
DEST
EffectiveAddress(SRC); (* 16-bit address *)
ELSE IF OperandSize = 16 AND AddressSize = 32
THEN
temp
EffectiveAddress(SRC); (* 32-bit address *)
DEST
temp[0..15]; (* 16-bit address *)
ELSE IF OperandSize = 32 AND AddressSize = 16
THEN
temp
EffectiveAddress(SRC); (* 16-bit address *)
DEST
ZeroExtend(temp); (* 32-bit address *)
ELSE IF OperandSize = 32 AND AddressSize = 32
THEN
DEST
EffectiveAddress(SRC); (* 32-bit address *)
FI;
FI;
Opcode
Instruction
Description
8D /
r
LEA
r16,m
Store effective address for
m
in register
r16
8D /
r
LEA
r32,m
Store effective address for
m
in register
r32
Table 2-16.
LEA Address and Operand Sizes
Operand Size
Address Size
Action Performed
16
16
16-bit effective address is calculated and stored in requested 16-bit
register destination.
16
32
32-bit effective address is calculated. The lower 16 bits of the address
are stored in the requested 16-bit register destination.
32
16
16-bit effective address is calculated. The 16-bit address is
zero-extended and stored in the requested 32-bit register destination.
32
32
32-bit effective address is calculated and stored in the requested
32-bit register destination.
Summary of Contents for ITANIUM ARCHITECTURE
Page 1: ......
Page 7: ...402 Intel Itanium Architecture Software Developer s Manual Rev 2 3 ...
Page 199: ...4 192 Volume 4 Base IA 32 Instruction Reference FWAIT Wait See entry for WAIT ...
Page 352: ...Volume 4 Base IA 32 Instruction Reference 4 345 ROL ROR Rotate See entry for RCL RCR ROL ROR ...
Page 589: ...4 582 Volume 4 IA 32 SSE Instruction Reference ...
Page 590: ...Index Intel Itanium Architecture Software Developer s Manual Rev 2 3 Index ...
Page 591: ...Index Intel Itanium Architecture Software Developer s Manual Rev 2 3 ...
Page 603: ...INDEX Index 12 Index for Volumes 1 2 3 and 4 ...
Page 604: ......