IBM 3745 Series, Hardware Maintenance Reference

Page: 78 / 712

X
'
77
'
Input: Adapter Level 2, 3,
4 Interrupt Requests Output: Miscellaneous
Control
Byte X, Bit 0
1
2
3
4
5
6
7
Byte 0, Bit 0
1
2
3
4
5
6
7
Byte 1, Bit 0
1
2
3
4
5
6
7
0
0
0
0
0
0
0
0
Not used
Level 2 bus 1 priority
Level 2 on bus 1
Not used
0
0
0
0
Level 3 bus 1 priority
Not used
Level 3 on bus 1
Not used
0
0
0
0 Not significant
Not significant
Not significant
Not significant
Not significant
Not significant
Not significant
Not significant
Reset IPL level 1 and not init.bit
Reset CCU hard checks
Reset MOSS panel inter.req.level 3
Reset MOSS diag request level 3
Reset MOSS SVC request level 3
Reset MOSS SVC response level 4
Reset PCI level 2
Reset MOSS inoperative level 1
Reset interval timer level 3
Reset PCI level 3
Reset MOSS level 2 diagnostic request
Reset address compare level 1
Reset program errors
Reset PCI level 4
Reset SVC level 4
Byte 0 pertains to level 2 and byte 1 to level 3. The priority bits in byte 0 for level 2
are independent of those in byte 1 for level 3.
Notes:
1. The following description applies to either byte.
One of the priority bits in a byte will be set ON if and only if one or both of the
bus interrupt bits in that byte are ON. However, the priority will be set one
cycle after the interrupt bit(s) is set, therefore there is a 1-cycle window in
which either or both interrupt bits can be ON without either priority bit.
This window occurs at the time interrupts are sampled from the adapter bus,
not necessarily at input X'77' time, but may affect the result of input X'77'.
To avoid this window, it is recommended that the program use input X'77' in
any one of the following ways.
a. Test only the priority bits in the appropriate byte, ignoring the interrupt bits.
This will insure that single and simultaneous bus interrupts will be serviced
in turn without the possibility of missed interrupts or ambiguity. In this
case, there is no restriction on when input 77 may be performed.
b. Test only the interrupt bits, ignoring the priority bits (in this case, the
program would have to decide by other means which interrupting bus to
service). There is no restriction on when input X'77' may be performed.
c. If neither procedure above is used, the use of the input X'77' instruction is
restricted, as follows: input X'77' should be performed in level 2 or level 3
only if there are no adapter interrupt(s) for that level.
2-36
IBM 3745 Models 130, 150, 160, 170, and 17A: Hardware Maintenance Reference