IBM 3745 Series Hardware Maintenance Reference Download Page 538

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POWER BER

ELD DETAIL

SEL#:hhhh FLAG:hh DATE:dd/dd TIME:dd:dd TYPE:ð4 ID:ðA
<ERROR DESCRIPTION>

<REFER.CODE IN CHAR.> CCCCCCCC

OLD

NEW

bbbbbbbb bbbbbbbb

===>

F1:END F2:MENU2 F3:ALARM F4:SUMMARY F5:LIST F7:PREVIOUS F8:NEXT

Power BER Type 04 - IDs 17, 35 and 36: Format foP5, see page 11-132.

ELD DETAIL

SEL#:hhhh FLAG:hh DATE:dd/dd TIME:dd:dd TYPE:ð4 ID:ðA
<ERROR DESCRIPTION>

<REFER.CODE IN CHAR.> CCCCCCCC

===>

F1:END F2:MENU2 F3:ALARM F4:SUMMARY F5:LIST F7:PREVIOUS F8:NEXT

Power BER Type 04 - IDs 20 to 23: These BER display a single line of informa-
tion, indicating the type of error, according to the next list:

ID 20

Power control detected error on MOSS reset

ID 21

Power control detected error on MMIO

ID 22

Power control detected error on RPO signal

ID 23

Power control detected error on CCU reset

One of those BER is generated when the corresponding lines is found every time
clamped to the same level.

Power BER Type 04 - IDs 28, 29: Format foP2, see page 11-132.

ELD DETAIL

SEL#:hhhh FLAG:hh DATE:dd/dd TIME:dd:dd TYPE:ð4 ID:hh
<ERROR DESCRIPTION>

<REFER.CODE IN CHAR.> CCCCCCCC

IML SOURCE:hh CAUSE:hh REASON:hh
CONTROL MODE:hh INSTAL TYPE:hh

===>

F1:END F2:MENU2 F3:ALARM F4:SUMMARY F5:LIST F7:PREVIOUS F8:NEXT

Power BER Type 04 - ID 30: Format foP3, see page 11-132.

11-126

IBM 3745 Models 130, 150, 160, 170, and 17A: Hardware Maintenance Reference

Summary of Contents for 3745 Series

Page 1: ...IBM 3745 Communication Controller Models 130 150 160 170 and 17A IBM Hardware Maintenance Reference SY33 2066 4 ...

Page 2: ......

Page 3: ...IBM 3745 Communication Controller Models 130 150 160 170 and 17A IBM Hardware Maintenance Reference SY33 2066 4 ...

Page 4: ...below A form for readers comments appears at the back of this publication If the form has been removed address your comments to IBM France Centre d Etudes et Recherches Service 0797 BP 79 06610 La Gaude France FAX 33 93 24 77 97 EMAIL FRIBMQF5 at IBMMAIL IBM Internal Use LGERCF at LGEPROFS When you send information to IBM you grant IBM a non exclusive right to use or distribute the information in ...

Page 5: ...ent 1 20 Maintenance 1 24 Chapter 2 Central Control Unit CCU 2 1 General Description 2 4 Functional Description 2 5 CCU Environment 2 12 Main Storage 2 13 CCU to Storage Interconnection 2 17 CCU to and from Adapters 2 20 CCU to and from MOSS 2 43 CCU Diagnostics 2 43 Performance Test Points 2 50 Chapter 3 Buses 3 1 Generalities 3 4 Bus Propagation Cards BPC1 BPC2 3 29 3746 900 3745 Attachment 3 30...

Page 6: ...lds 5 31 Problem Determination Aid 5 37 Communication Interfaces 5 40 Chapter 6 The Token Ring Subsystem 6 1 Token Ring Network 6 4 The Token Ring Adapter in the 3745 6 10 Token Ring Interface Coupler TIC Card 6 12 Token Ring Multiplexor TRM Card 6 15 TRA Resets 6 19 Error Detection and Reporting 6 20 Problem Determination Aid 6 27 Chapter 7 Channel Adapter CA 7 1 Introduction 7 4 CA Operating Env...

Page 7: ...11 11 Specific Mechanisms 11 12 AutoMaint 11 16 BER Recovery Procedures 11 24 Unresolved Interrupts 11 25 MOSS Error Logging 11 29 MOSS BERs Used With the IPL Application 11 33 Diagnostics BER Type 03 11 123 Power BER Type 04 11 125 NCP ESS BER Type 08 11 133 NCP 3746 Model 900 BER Type 9 11 145 NCP CA BER Type 10 11 164 NCP TSS HPTSS BER Type 11 11 179 NCP PEP BER Type 12 11 191 NCP CCU BER Type ...

Page 8: ...tation for the 3745 Models 130 150 160 170 and 17A and 3746 Model 900 X 9 Service Documentation for the 3745 Models 130 150 160 170 and 17A and 3746 Model 900 X 13 Index X 17 vi IBM 3745 Models 130 150 160 170 and 17A Hardware Maintenance Reference ...

Page 9: ...mits for a Class A digital device pursuant to Part 15 of the FCC Rules These limits are designed to provide reasonable protection against harmful interference when the equipment is operated in a commercial environment This equipment generates uses and can radiate radio frequency energy and if not installed and used in accordance with the instruction manual may cause harmful interference to radio c...

Page 10: ...he standard set by Voluntary Control for Interference by Data Processing Equipment and Electronic Office Machines VCCI with an aim to prevent radio interference in commercial and industrial districts This equipment could cause interference to radio and television receivers when used in and around residential districts Please handle the equip ment properly according to the instruction manual Korean...

Page 11: ...rks The following terms denoted by an asterisk used in this publication are trade marks or service marks of IBM Corporation in the United States or other countries ESCON IBM LPDA MVS NetView OS 2 PS 2 RETAIN VES VTAM Notices ix ...

Page 12: ...x IBM 3745 Models 130 150 160 170 and 17A Hardware Maintenance Reference ...

Page 13: ...ce personnel check whether the 3745 conforms to IBM safety criteria They have to be used each time the 3745 safety is suspected The Service Inspection Procedures section is located at the beginning of the 3745 Maintenance Information Procedures MIP manual SY33 2070 The 3745 areas and functions checked through service inspection procedures are 1 External covers 2 Safety labels 3 Safety covers and s...

Page 14: ...xii IBM 3745 Models 130 150 160 170 and 17A Hardware Maintenance Reference ...

Page 15: ... circuit terminating equipment modems autocall units and so on and the terminals that attach to 3745s Be familiar with the host channel to which the 3745 can be attached Service Personnel Definitions See Maintenance Information Procedures MIP SY33 2070 manual How to Use the Maintenance Library Maintenance on the 3745 is performed only when a failure or suspected failure occurs in the machine The c...

Page 16: ... should contact the HCS for assistance since the problem may require special tools or techniques that are described in the Hardware Maintenance Reference and Service Functions manuals and are applied by a Product Support Trained CE Where to Find More Information See Bibliography page X 9 xiv IBM 3745 Models 130 150 160 170 and 17A Hardware Maintenance Reference ...

Page 17: ... revised edition gives information concerning the 3745 Model 17A and on the 3746 Model 900 connection This edition also corrects minor errors or omissions without the addition of revision bars Copyright IBM Corp 1989 1994 xv ...

Page 18: ...xvi IBM 3745 Models 130 150 160 170 and 17A Hardware Maintenance Reference ...

Page 19: ...e 1 7 Control Subsystem CSS 1 7 Communication Subsystem 1 8 Low Medium Speed Transmission Subsystem TSS 1 9 High Performance Transmission Subsystem HPTSS 1 12 Ethernet Subsystem ESS 1 13 Token Ring Subsystem TRSS 1 14 Maintenance and Operator Subsystem MOSS 1 15 Programming Support and Network Management 1 20 Host Resident Programs 1 20 Controller Resident Programs 1 22 Generating and Loading the ...

Page 20: ...d lines and their associated DCEs c Local clusters and terminals directly attached without DCE d Remote clusters and terminals via stand alone DCEs and telecommuni cation facilities switched or non switched e Remote communication controllers clusters terminals via X 25 public data networks f Remote communication controllers clusters terminals via integrated DCEs and 4 wire nonswitched telecommunic...

Page 21: ...3745 Models 130 150 160 and 170 Data Flow Chapter 1 General Information 1 3 ...

Page 22: ...745 Model 17A Data Flow For model 17A DMA and IOC buses are connected to the CBC in the 3746 900 This MLA card links the MOSS to the Service Processor through a LAN 1 4 IBM 3745 Models 130 150 160 170 and 17A Hardware Maintenance Reference ...

Page 23: ...er LSS 1 High speed scanner HSS 1 Ethernet LAN adapter ELA 1 Token ring adapter TRA 32 Low medium speed lines 16 integrated DCEs 14 4 kbps 3 integrated DCEs 56 kbps 3745 Model 160 0 CA 2 low speed scanners LSS 2 High speed scanners HSS 2 Ethernet LAN adapters ELA 1 Token ring adapter TRA 32 Low medium speed lines 3745 Model 170 4 CAs 6 low speed scanners LSS 1 Token ring adapter TRA 2 High speed s...

Page 24: ...storage ALL 1 ð1G A1 X2 LSS adapter 15ð 1 ð1G A1 Q2 LIC Unit LIB1 or LIB2 15ð 1 ð1M A2 LSS adapter Note 1 with a 16ð 1 ð1G A1 Q2 LIC unit LIB1 1 ð1M A2 HSS adapter Note 1 16ð 1 ð1G A1 T2 and U2 ESS adapter Note 1 16ð 1 ð1G A1 T2 and U2 TRSS adapter Note 1 16ð 1 ð1G A1 J2 K2 and L2 Notes 1 These adapters are mutually exclusive on Model 160 1 6 IBM 3745 Models 130 150 160 170 and 17A Hardware Mainte...

Page 25: ...nctional areas Control Subsystem CSS The control subsystem contains The central control unit CCU with its associated high speed buffer HSB The main storage The storage control equipped with a direct memory access DMA Chapter 1 General Information 1 7 ...

Page 26: ...pter BCCA The input output control bus IOC bus The DMA bus The MOSS input output control bus MIOC bus Communication Subsystem Four types of line connection are used to connect data communication lines The low medium speed transmission subsystem TSS The high performance transmission subsystem HPTSS The Ethernet subsystem ESS The token ring subsystem TRSS 1 8 IBM 3745 Models 130 150 160 170 and 17A ...

Page 27: ...onsists Up to six low speed scanners LSS Up to four LIC boards LIBs Low Speed Scanner A low speed scanner consists of one card housing a communication scanner processor CSP associated to a front end scanner low speed FESL Chapter 1 General Information 1 9 ...

Page 28: ...C Board LIB There are up to four LIC boards LIB Each LIB houses One multiplexer MUX and Up to eight line interface couplers LICs 1 10 IBM 3745 Models 130 150 160 170 and 17A Hardware Maintenance Reference ...

Page 29: ...face Couplers LICs There are six types of LIC namely LIC1 LIC3 LIC4A and LIC4B for attaching to Local direct attached terminals no DCEs Remote terminals via standalone DCEs and telecommunication facilities An internal clock function ICF is available on these LICs to provide clocking signals to non clocked DTEs or DCEs LIC5 and LIC6 both housing integrated DCEs providing direct access to the teleco...

Page 30: ...e HPTSS consists of up to two high speed scanners HSS Each HSS consists of a communication scanner processor CSP card associated with a front end scanner high speed FESH card 1 12 IBM 3745 Models 130 150 160 170 and 17A Hardware Maintenance Reference ...

Page 31: ...ubsystem ESS The ESS consists of up to two Ethernet LAN adapters ELA Each ELA consists of a communication scanner processor CSP card associated with an Ethernet adapter card EAC Chapter 1 General Information 1 13 ...

Page 32: ...S consists of one token ring multiplexer TRM driving two token ring inter face couplers TICs providing access to two IBM token rings operating at 4 or 16 Mbps 1 14 IBM 3745 Models 130 150 160 170 and 17A Hardware Maintenance Reference ...

Page 33: ...s Operating mode management Line configuration management Controller supervision Controller concurrent diagnostic Online event recording and error notification including for the integrated DCEs Problem determination error in the network including the controller Failure isolation and repair error in the controller Remote support facility link management The MOSS continuously monitors the status of ...

Page 34: ...remote support facility is used it allows communication between the MOSS and the IBM RETAIN system providing remote service facility RSF The RETAIN terminal can be used as an operator console as well as for transferring microcode patches to the MOSS if required Refer to 3745 Models 130 150 160 and 170 Operator Consoles on page 1 17 The 3745 Model 17A uses a LAN attached console service processor R...

Page 35: ...hich is mandatory and A remote or an alternate console It also provides attachment for the remote support facility RSF The consoles and RSF are connected to the MOSS via a common communication adapter Only one console can be active at a time Three types of password enable access to the MOSS from a local remote or alter nate console and for remote IBM maintenance via RSF Chapter 1 General Informati...

Page 36: ...4 1 LAN attached console OS 2 with DCAF 2 Remote console via user network PS 2 with DCAF See Note 3 RSF console via PSN OS 2 with DCAF 4 RETAIN console 5 Access method console 6 NetView console Note If no 3746 900 is installed the service processor must be connected to the 3745 through a TIC2 for the use of the remote console 1 18 IBM 3745 Models 130 150 160 170 and 17A Hardware Maintenance Refere...

Page 37: ...r 3 Powered ON by the operator and OFF by a remote SNA command 4 Powered ON through the scheduled power ON MOSS function 5 Re powered ON automatically by the auto restart function after a power outage 6 Re powered ON automatically by a retry function after a power supply or fan problem Chapter 1 General Information 1 19 ...

Page 38: ...ons Access Method BTAM BTAM Extended Support BTAM ES Remote Terminal Access Method RTAM System Support Programs Advanced Communications Function for System Support Programs SSP in an MVS environment Advanced Communications Function for System Support Programs in MVS VM and VSE environments SSP is used to generate the 3745 control program In addition SSP provides utilities for loading dumping and t...

Page 39: ... s interface to VTAM in a data communication network A session monitor which enables the user to examine from a central control point information related to the SNA network and to identify network problems A hardware monitor which helps the user to get problem determination infor mation that is generated at resources that are either link attached or channel attached to the host system As a cohesiv...

Page 40: ...tion from and to EBCDIC For the BSC protocol this support and translation operation is performed by the scanners NCP includes the token ring interconnection functions NCP coexists with the following IBM licensed programs Network Routing Facility NRF Network Terminal Option NTO X 25 NCP Packet Switching Interface NPSI X 25 SNA Interconnection XI X 21 Short Hold Mode Multiple Port Sharing X 21 SH MP...

Page 41: ...trol Program Load VTAM and the 3745 MOSS allows the automatic IPL dump capability For an auto matic IPL from the controller disk the network operator must have assigned this option during NCP loading Coexistence and Migration The 3745 running under NCP can coexist with other IBM communication control lers The 3745 supports networks based on the earlier IBM 2701 Data Adapter Unit IBM 2702 Transmiss...

Page 42: ...for battery replacement and provides the CE with a reference code The Maintenance Information Procedures MIP SY33 2070 guides the mainte nance personnel for replacement procedures Maintenance Aids Tools and Test Equipment Refer to Appandix A 1 24 IBM 3745 Models 130 150 160 170 and 17A Hardware Maintenance Reference ...

Page 43: ... Subsystem Power ON Reset POR 2 13 Main Storage 2 13 Storage Environment 2 14 Direct Memory Access and Storage Control SCTL 2 14 CCU to Storage Interconnection 2 17 Cache Storage 2 17 Storage Protection 2 18 CCU Timers 2 19 CCU to and from Adapters 2 20 IOC Control Logic 2 20 IOC Data Flow 2 20 Registers 2 21 Hardware Registers 2 42 CCU to and from MOSS 2 43 CCU Diagnostics 2 43 CCU Error Handling...

Page 44: ...The CCU in 3745 Models 130 150 160 and 170 Data Flow 2 2 IBM 3745 Models 130 150 160 170 and 17A Hardware Maintenance Reference ...

Page 45: ... Flow Figure 2 1 The CCU in 3745 Model 17A Data Flow For model 17A DMA and IOC buses are connected to the CBC in the 3746 900 This MLA card links the MOSS to the Service Processor through a LAN Chapter 2 Central Control Unit CCU 2 3 ...

Page 46: ... 32 Kbytes PUC 5 Oscillator CCU MIOC MIOC Bus Control 5 to MOSS Power 5 IOC Supplies Control 6 6 DMA Bus IOC Bus Packaging See YZ pages for locations The communication subsystem CSS includes the following components Processor unit card PUC Storage basic card STO 4 or 8 Mbytes Storage control card SCTL 2 4 IBM 3745 Models 130 150 160 170 and 17A Hardware Maintenance Reference ...

Page 47: ...y input or output halfword IOH or input or output halfword immediate IOHI instructions in the CCU AIO mode The operation uses cycle steal for data exchange between adapters and main storage without control program intervention One bus IOC gives access to the adapters environment Communicates with the MOSS through the MOSS IOC MIOC The operations performed can be direct or indirect MIOH MIOHI MOSS ...

Page 48: ... general registers is loaded with the bits corresponding to those program levels to be masked Output instruction X 7E set mask register is then executed using the general register as input to the mask register To selectively unmask one or more program levels the same procedure is followed except that the output X 7F reset mask register instruc tion is executed Interrupts The communication controll...

Page 49: ...errupt Requests A particular interrupt request latch can be set as a result of a hardware detected condition or in some cases by the program through the execution of an output instruction The latch can be reset by one of several output instructions depending upon the specific interrupt request The procedures for setting and resetting individual adapter interrupt requests are described in the adapt...

Page 50: ...k level 1 IPL request level 1 MOSS inoperative level 1 Hard error level 1 Note 1 I O parity error I O time out error Interrupt Level 2 Adapter level 2 request LA Program controlled interrupt level 2 MOSS diagnostic level 2 Interrupt Level 3 Adapter level 3 request CA MOSS diagnostic level 3 Interval timer level 3 Program controlled interrupt level 3 Panel interrupt request level 3 Interrupt Level ...

Page 51: ... Program Level 3 Hardware Starting address in LS 42 C and Z latches for level 3 Note 2 General register group 1 Exit instruction register addresses X ð8 to ðF Return address from interrupted level 4 6 from reg X 1ð IAR Program Level 4 Hardware Starting address in LS 43 C and Z latches for level 4 Note 2 General register group 2 Exit instruction register addresses X 1ð to 17 Return address when no ...

Page 52: ...atch 1 ð ð 1 1 T 2 4 BZL Branch on Z latch 1 ð ð ð 1 3 4 BCT Branch on count 1 ð 1 1 1 1 T 2 4 BB Branch on bit 1 1 M M 1 M 1 LRI Load register immediate 1 ð ð ð ð 1 ARI Add register immediate 1 ð ð 1 ð 1 SRI Subtract register immediate 1 ð 1 ð ð R N I 1 CRI Compare register immediate 1 ð 1 1 ð 1 XRI Exclusive OR register immediate 1 1 ð ð ð 1 ORI OR register immediate 1 1 ð 1 ð 1 NRI AND register...

Page 53: ...LR Load register ð ð 1 ð ð ð 1 ð ð ð 1 3 AR Add register ð ð 1 ð ð 1 1 ð ð ð 1 3 SR Subtract register ð ð 1 ð 1 ð 1 ð ð ð 1 3 CR Compare register ð ð 1 ð 1 1 1 ð ð ð 1 3 XR Exclusive OR register ð ð 1 1 ð ð 1 ð ð ð 1 3 OR OR register ð ð 1 1 ð 1 1 ð ð ð 1 3 NR AND register ð ð 1 1 1 ð 1 ð ð ð 1 3 LOR Load with offset register ð ð 1 1 1 1 1 ð ð ð 3 BALR Branch link register ð R2 ð R1 ð 1 ð ð ð ð ð ...

Page 54: ...a read from storage is written directly into one or more CCU registers and or in local storage Main storage is read and written across the storage data bus bidirectional 36 bits wide which is the only port to from main storage for the whole machine MIOC Interconnection Through the MIOC interface the MOSS will be able to obtain or alter the state of 3745 IOC Bus This is a multipurpose compatible bu...

Page 55: ...nal the following sequence of warm up storage is started 1 Clear all latches and counters 2 Then perform 128 cycles to initialize storage 3 Perform one cycle to configure storage type and size 4 Then blank storage with proper ECC During all that time incoming requests are inhibited Main Storage The main storage contains the control program It is packaged on one card of 4 or 8 Mbytes The storage wo...

Page 56: ...CCU via the cache storage and high speed adapters via the DMA function of the SCTL Control the different storage operations and ensure data transfer integrity CCU read and write Write requests are buffered in SCTL so that the CCU and the storage oper ations can overlap Cache storage line loading DMA burst transfers The data is aligned and temporarily stored in a buffer so as to optimize the use of...

Page 57: ...speed adapters are hooked It receives requests from the high speed adapters It performs data alignment reads or writes its DMA buffer and makes storage requests to the MCTL and ECC During a DMA write storage transfer it makes requests to the CCUI logic for cache line invalidations and for access to the DMA storage protect RAM MCTL and ECC The MCTL and ECC interconnects the storage It receives stor...

Page 58: ... E SCTL Error 5 Line Inval High speed buffer CCU Error 5 Line Xfer LSSD 5 6 6 6 6 S Address 25 S C A R Data 36 T 5 5 Byte Select 4 L C Storage Go Storage Grant 6 C 5 Read Write U Stg Prot Write Inhibit Stg User ID 3 Clocks 7 Stg Size Installed In 7ð Stg Control Out 74 Stg Error 1 and 2 2 5 LSSD 3 5 Storage Control Mode See the output X 74 instruction on page 2 30 2 16 IBM 3745 Models 130 150 160 1...

Page 59: ...an either write one byte one halfword or one fullword However the cache is always loaded from storage with 16 contiguous bytes forming a line The 32K cache is made of 2048 x 16 byte lines and its direc tory is two set associative Cache organization is thus 1024 rows x 2 sets x 16 bytes The following table summarizes the various cache data path functions Request Storage User Cache Function Manageme...

Page 60: ...y from memory to the CCU without cache involvement Line Invalidation Because of DMA operation the SCTL requests the cache to invalidate a line An invalidation request has priority over a CCU request When a line invalidation is requested the SCTL raises the line invalid line which instructs the cache not to propagate the storage address register SAR to the storage address data SAD bus and to latch ...

Page 61: ... keys are located in a local storage storage key RAM and the user keys are located in registers To perform the necessary initialization the program must execute output X 73 instructions for setting the storage keys for all installed 4 Kbyte blocks of storage and up to 6 output X 73 instructions for setting the user keys CCU Timers Two timers are available in the CCU They are the 100 ms interval ti...

Page 62: ...it is loaded by the R1 field In AIO operations it contains the cycle steal address The IOC bus operations are under the control of the IOC control logic using a handshaking protocol between the CCU and the adapters Level 2 and Level 3 Interrupt Reporting IOC byte 1 bit 0 produces a single CA level 3 interrupt request to the CCU IOC byte 0 bit 1 produces a single LA level 2 interrupt request to the...

Page 63: ... associated with the active program level The registers within the currently active group are directly addressable with program instructions The control program can access the general registers by specifying them as external registers in input and output instructions Instruction Address Register General register 0 in each group is the instruction address register IAR This register is an implied ba...

Page 64: ... registers Each group is associated to one program level The hardware registers Seven work registers Instruction address register IAR Lagging address register LAR See Hardware Registers on page 2 42 for details Hardware latches The following tables list the input and output instructions 2 22 IBM 3745 Models 130 150 160 170 and 17A Hardware Maintenance Reference ...

Page 65: ... IOHI BAL instruction Holding register for MOSS IOH Holding register for IOHI Not used Not used Storage size installed Operator address or data entry register Operator function select controls Read SP AE key LAR AIO CCW IOC level 1 interrupt requests Adapter level 2 3 or 4 interrupt requests Not used Utility High resolution timer value Branch trace address pointer Branch trace buffer count CCU har...

Page 66: ... use Not used Zero register Holding register for IOH IOHI BAL instruction Holding register for MOSS IOH Holding register for IOHI Not used Not used Hard stop Display register 1 Display register 2 Write select SP AE key Storage control Not writable Miscellaneous control Miscellaneous control Not used Utility Resolution utilisation counter control Set PCI level 2 Set PCI level 3 Set PCI level 4 Set ...

Page 67: ...e the input instruc tion this might not be true in case of error Refer to Principles of Operations Manual for more information Input X 75 AIO channel control word This instruction loads a general register with bits of the CCW received by the IOC for an AIO which has been suspended or stopped due to an error detected by the hardware Otherwise the data loaded in this general register is NOT valid In...

Page 68: ... register 1 Output X 72 display register 2 This instruction causes the contents of the general register to be loaded into display register 2 Output X 73 read storage protection or address exception register This instruction causes the contents of the general register to be used to address and or set the storage and protect keys Output X 74 storage control This instruction causes the contents of th...

Page 69: ...ective Output X 7D set PCI level 4 This instruction causes a program controlled interrupt request to be set for program level 4 PCI level 4 This allows a program level to transfer a proc essing requirement to a lower priority level The bit settings of the general reg ister are ignored A PCI interrupt request is immediately effective Output X 7E set mask bits This instruction causes the mask bits o...

Page 70: ...Byte 0 Bit 0 1 2 3 4 5 6 7 Byte 1 Bit 0 1 2 3 4 5 6 7 0 0 0 0 0 0 0 0 I I I I Bit setting depending I on storage size I See Table below I I 0 0 0 0 0 0 0 0 Ignored Ignored Ignored Ignored Ignored Ignored Ignored Ignored Ignored Ignored Ignored Ignored Ignored Ignored Ignored Ignored Ignored Ignored Ignored Ignored Ignored Ignored Ignored Ignored Storage Size Storage Card Input Byte 0 Bits 0 1 2 3 ...

Page 71: ... Operator Function Select Control Output Program Display Register 2 DR2 Byte X Bit 0 1 2 3 4 5 6 7 Byte 0 Bit 0 1 2 3 4 5 6 7 Byte 1 Bit 0 1 2 3 4 5 6 7 0 0 0 0 0 0 0 0 Function select 8 Function select 9 Function select A Storage address Register address Function select B Function select C Function select D Function select E Function select 1 Function select 2 Function select 3 Function select 4 ...

Page 72: ...it 0 UKA bit 1 UKA bit 2 UKA bit 3 UKA bit 4 Ignored Enable SP or AE I 00 user key 10 exception key I 01 stor key 11 read only key Modify key value Key value bit 0 Key value bit 1 Key value bit 2 X 74 Input Lagging Address Register LAR Output Storage Control Byte X Bit 0 1 2 3 4 5 6 7 Byte 0 Bit 0 1 2 3 4 5 6 7 Byte 1 Bit 0 1 2 3 4 5 6 7 LAR Byte X Bit 0 1 2 3 4 5 6 7 LAR Byte 0 Bit 0 1 2 3 4 5 6 ...

Page 73: ...ly mode NO refresh mode Force storage errors Force storage errors Force storage errors Force storage errors Force storage errors Force storage errors X 1 1 0 1 X X X X 1 0 1 1 X X X MCTL functions 0 1 1 1 1 X X 0 0 1 1 1 1 X X 1 0 1 X X 1 X 1 X 1 1 X X 1 0 0 0 Force Y 7 at 0 1 1 X X 1 0 1 0 Force Y 7 at 1 1 1 X X 1 1 0 0 Force Y 7 X 7 at 0 1 1 X X 1 1 1 0 Force Y 7 X 7 at 1 1 1 X X 1 1 0 1 Force Y...

Page 74: ...Notes 1 Bit 0 0 AIO from CAs Bit 0 1 AIO from LAs 2 Bits 1 to 4 are either pointer number if bit 0 0 or LAs address if bit 0 1 2 32 IBM 3745 Models 130 150 160 170 and 17A Hardware Maintenance Reference ...

Page 75: ...1 2 3 4 Number TRA 1 ð ð ð ð ð1 TRA 1 ð ð ð 1 ð2 LSS HSS ESS 1 ð ð 1 ð ð3 LSS HSS ESS 1 ð ð 1 1 ð4 LSS 1 ð 1 ð ð ð9 LSS 1 ð 1 ð 1 1ð LSS 1 ð 1 1 ð 11 LSS 1 ð 1 1 1 12 CA ð ð ð ð ð ð5 CA ð ð ð ð 1 ð6 CA ð ð ð 1 ð ð7 CA ð ð ð 1 1 ð8 Chapter 2 Central Control Unit CCU 2 33 ...

Page 76: ...cep I See IOC Storage protec I Note IOC Invalid CCW I 0 IOC Timout IOC Bus in parity IOC Adapter init operation IOC MOSS init operation Not used Not used Not used 0 Not used Not used Not used Not used Not significant Not significant Not significant Not significant Not significant Not significant Not significant Not significant Reset IOC errors Not significant Start branch trace mode CCU prog reque...

Page 77: ...IO CCW S L or D I D or D I D WR I O tag is OFF VH must rise last AIO transfer data read is on byte boundary No No response to TD for AIO pointer initialization No VH didn t fall after TD fall for AIO pointer initialization I O tag is OFF VH must rise IOH end or AIO end after data exchange No No No CCW parity error AIO data read or channel pointer register read 2nd transfer Bus in parity error on A...

Page 78: ... if one or both of the bus interrupt bits in that byte are ON However the priority will be set one cycle after the interrupt bit s is set therefore there is a 1 cycle window in which either or both interrupt bits can be ON without either priority bit This window occurs at the time interrupts are sampled from the adapter bus not necessarily at input X 77 time but may affect the result of input X 77...

Page 79: ...rogram level 4 interrupted 1 Program level 5 interrupted 1 0 0 0 0 Not significant Not significant Not significant Not significant Not significant Not significant Not significant Not significant Not significant Not significant Set program IPL request Not significant Remote power OFF Inhibit program level 5C and Z latches Program level 5C latch Program level 5Z latch Not significant Not significant...

Page 80: ...it 0 1 2 3 4 5 6 7 Branch trace address bit X 0 Branch trace address bit X 1 Branch trace address bit X 2 Branch trace address bit X 3 Branch trace address bit X 4 Branch trace address bit X 5 Branch trace address bit X 6 Branch trace address bit X 7 Branch trace address bit 0 0 Branch trace address bit 0 1 Branch trace address bit 0 2 Branch trace address bit 0 3 Branch trace address bit 0 4 Bran...

Page 81: ...t 0 1 2 3 4 5 6 7 Byte 1 Bit 0 1 2 3 4 5 6 7 0 0 0 0 0 0 0 0 Note Not significant Not significant Not significant Not significant Not significant Not significant Not significant Not significant Not significant Not significant Not significant Not significant Not significant Not significant Not significant Not significant Not significant Not significant Not significant Not significant Not significan...

Page 82: ...arity error Cache internal error A B bus parity error D1 register parity error Not significant SAR parity error ROS parity error Z register parity error D2 register parity error Not significant Not significant Not significant Not significant Not significant Not significant Not significant Not significant Not significant Not significant Not significant Not significant Not significant Not significan...

Page 83: ...cant IPL level 1 Not significant Not significant Not significant Not significant Not significant Not significant Not significant Not significant Not significant Not significant Not significant Not significant Not significant Not significant Not significant Not significant Not significant Not significant Adapter level 1 request Level 2 request Level 3 request Level 4 request Program level 5 executi...

Page 84: ... Address Register IAR See General Registers above Lagging Address Register LAR The LAR is loaded from the IAR at the begin ning of each instruction execution The lagging address register is a came from register When displayed by the operator or by the program using input X 74 or MOSS indirect input X 74 it contains the address of the last instruction executed prior to the instruction that is curre...

Page 85: ... instruction Maintenance Temporary Address Register MTAR This register in local storage LS address X 7E contains the main storage address used by any opera tion initiated by the program running in MOSS and involving main storage Maintenance Temporary Data Register MTDR This register in local storage LS address X 7F contains information read out of main storage for the operations described for the ...

Page 86: ... 1 bit 1 set to 1 MOSS Program CCU Mode Result Bypass Bypass Bus stop 1 Bus stop 1 Bus stop and bypass Bypass Bypass Bypass Normal 2 Bypass Bypass Bypass Normal 2 Normal 2 Bypass CCU Error Handling The following are the basic principles of the CCU error handling strategy CCU Detected Hardware Errors They are high severity errors usually hardware failures They stop the CCU No retry is performed The...

Page 87: ...s Inter No 6 Yes to MOSS MIOH No 6 Queue Halt to Error CCU Level 1 5 Interr CSP Hardcheck Entered Level 1 Bus Error Yes 6 No No 6 Prog High Level 6 Error Int to MOSS Interrupt Level 1 Level 1 Level 1 5 Queued to Prog No Entered Yes to NCP Notes CCU hard check results in stopping the program AIOs and branch trace Bus error without adapter interface check stop mode Chapter 2 Central Control Unit CCU...

Page 88: ...ng its contents to the OP register SAR Parity Error Parity error detected in the storage address register at any time For other parity errors see CCU Hard Errors on page 2 39 Notes 1 At storage initialization time unrecoverable storage errors are inhibited and storage write operations are not prevented when ECC disable is set see OUT X 74 2 A CCU clock check is also provided This check activates a...

Page 89: ...any of the 53 valid OP codes or input or output instruction to invalid external register addresses Handling These errors result in an interrupt level 1 sent to the control program except if already in program level 1 in this case a CCU hard check condition occurs Error information can be obtained by the control program using the input X 7E instruction see Input Instructions on page 2 25 However st...

Page 90: ...control program and a halt signal is sent to the adapter No level 1 interrupt will be issued to the MOSS by the LAs Error information can be obtained by the control program using input X 7E and input X 76 instructions The adapter address will be obtained by the program using the input X 75 instruc tion which allows sensing the CCW bits During MOSS AIOs These errors during an adapter AIO operation ...

Page 91: ... means Mask channel request for AIOs that is AIO stop is set MOSS Interconnection Type Errors MOSS Interconnection Parity Error Parity error detected either on MOSS address bus or on MOSS data bus during a write operation Parity error detected on MOSS address bus during a read operation MOSS OP Error Moss initiates an indirect operation while the CCU busy bit is ON meaning that CCU resources are a...

Page 92: ...hed IOC1 IO tag IOC1 AIO hold Not used Not used Spare pin Spare pin A30F00 A30F10 A30F20 A30F30 A30F40 A30F50 A30F60 A30F70 A30F80 A30F90 The performance test points TPs are located on the wiring side of the PUC card CCU The following figure will help in locating the test points A3ð Bðð Cðð Eðð 456789 123456789 12 6789 123456789 ðð6ððð ððððððððð ðð ðððð ððððððððð A3ð TPs Detail A Bottom Top B3ð Wi...

Page 93: ...ysical Address Wiring 3 31 CA Addressing 3 32 Line Adapter Addressing LSS HSS and ELA 3 34 3746 Model 900 Adapter Addressing CBC PRC 3 36 LIC Board Addressing 3 38 Line Addressing 3 39 Token Ring Adapter TRA Addressing 3 46 Token Ring Line Addressing 3 47 Adapter Bypass Mechanism 3 48 For Line Adapters 3 48 For Channel Adapters 3 48 Cycle Steal Grant CSG and Autoselection Mechanism for Model 170 3...

Page 94: ...The Buses in 3745 Models 130 150 160 and 170 Data Flow 3 2 IBM 3745 Models 130 150 160 170 and 17A Hardware Maintenance Reference ...

Page 95: ... 17A Data Flow Figure 3 1 The Buses in 3745 Model 17A Data Flow For model 17A DMA and IOC buses are connected to the CBC in the 3746 900 This MLA card links the MOSS to the Service Processor through a LAN Chapter 3 Buses 3 3 ...

Page 96: ...ending on whether the program initiates an operation PIO or the adapter initiates it AIO In both operations the A address and D data registers of the data flow con trolled by the IOC logic act as buffers between the CCU s and the adapters CAs and LAs The IOC bus carries interrupt requests from the adapters levels 1 2 and 3 when not busy with PIO or AIO operations IOC Bus Protocol Read PIO example ...

Page 97: ... 3 HSS ELA3 LSS 4 HSS ELA4 TERMD 1 LSS 9 LSS 1ð LSS 11 LSS 12 TRA 1 TRA 2 CA 5 CA 6 CA 7 CA 8 2 TERMR TERMC 2 TERMI 1 1 DMA and IOC buses are connected to the CBC in the 3746 900 if present for model 17A 2 Only on 3745 Model 17A Figure 3 2 CCU Bus Layout Chapter 3 Buses 3 5 ...

Page 98: ...t Low 1 CSGL x Input Output 1 I O x Halt 1 HLT x Out 1 R W x Valid Byte 1 VB x x Valid Halfword 1 VH x x End of Chain 1 EOC x x Modifier 1 M x x Parity Valid 1 PV x x CA IPL Detect 1 CAIPL x Reset Tag See Note 1 RST Data Byte ð 9 OUT DBð x IN DBð x x Data Byte 1 9 OUT DB1 x IN DB1 x x Scan Int See Note 2 SCI x Legend The contents of the parentheses indicate the number of wires in line function x S...

Page 99: ...U may now sample for interrupts Cycle Steal Request High CSRH A scanner activates CSRH whenever it wishes to start an AIO operation The scanner keeps CSRH active until it receives CSGH Cycle Steal Grant High Cycle Steal Request Low CSRL A channel adapter activates CSRL whenever it wishes to start an AIO operation The channel adapter keeps CSRL active until it receives CSGL Cycle Steal Grant Low Cy...

Page 100: ...e CCU may deactivate its control line All adapters will activate valid halfword when the CCU deactivates the I O line and deactivate valid halfword when the CCU activates the I O line The CCU will proceed with an IO operation after all adapters have deactivated valid halfword A selected adapter will activate the end of chain line instead of valid halfword for the last halfword transfer of an AIO o...

Page 101: ...e used for an additional function when the I O line is deacti vated as follows Byte 0 bit 1 LAs Level 2 interrupt request to CCU Byte 0 bit 5 CAs Level 1 interrupt request to CCU Byte 1 bit 0 CAs Level 3 interrupt request to CCU Byte 1 bit 5 LAs Level 1 interrupt request to CCU The adapters activate their interrupt requests to the CCU using these paths but only when the I O line is inactive The CC...

Page 102: ...s is routed from the SCTL card to the FESH EAC card s See Figure 3 4 for details Physical Interconnection Storage SCTL PUC DMA Bus FESH CSP EAC CSP TERMD 1 Figure 3 4 DMA Bus Physical Interconnection 1 DMA buses are connected to the CBC in the 3746 900 if present for model 17A 3 10 IBM 3745 Models 130 150 160 170 and 17A Hardware Maintenance Reference ...

Page 103: ...f wires in the line function Figure 3 5 DMA Bus Interconnection Layout DMA to SCTL Bus Line Function EAC Line Function SCTL FESH Request 1 x Grant 1 x Valid 1 x Read Write 1 x Data Bus 18 Out x In x Ready 1 x Byte Select 1 Out x In x Turnaround 1 x SCTL Clock 1 x FESH EAC Clock 1 x Error 3 x Legend The figure in parentheses indicates the number of wires in the line function x Signal from Figure 3 ...

Page 104: ...bus 18 bidirectional lines Used to transfer the CCU address and burst length from the selected adapter and to support the data transfers Ready It is an envelope of the actual data transfer if the ready bit is ON there is a data transfer Byte Select One bidirectional line Indicates that only one byte is transferred in the last halfword data transfer Turnaround Indicates a read data transfer SCTL Cl...

Page 105: ...lock H C A Delay D1 D3 D5 D7 D9 D11 D13 Dx H Data Bus ð H A A Delay D2 D4 D6 D8 D1ð D12 D14 Dy H Data Bus 1 Valid Ready Turnaround H H H Byte Select Error 3 A Address C Count D Data H High impedance driver 3 states Delay Delay to transfer data from storage Chapter 3 Buses 3 13 ...

Page 106: ... D3 D5 D7 Dx Delay H Data Bus ð H A A D2 D4 D6 D8 Dy Delay H Data Bus 1 Valid Ready Turnaround H H Byte Select Error 3 A Address C Count D Data H High impedance driver 3 states Delay Delay to transfer data to storage 3 14 IBM 3745 Models 130 150 160 170 and 17A Hardware Maintenance Reference ...

Page 107: ...tion decode 2 IOC initialization 3 Adapter addressing and selection 4 Data transfer Write from CCU Read to CCU At step 1 Instruction code 50 IOH with R1 and R2 Instruction code 70 IOHI with R1 and the second halfword of the instruction whose contents go into the D register PIO Initiated by the MOSS MIOH MIOHI instructions are equivalent to IOH IOHI instructions except that 1 The MOSS initiates the...

Page 108: ...quests IRR from all the R2 contents to B Reg adapters 5R2 ð 1 6 BUS CLEARED ð DBð DB1 5 5R1 ð 1 ð 1 7 8 B F Adapter R W 5 Address 6 Read 1 Write ð Cmd When all VH are dropped TA 5 DBð 1 read by adapter VH raised by selected adapter TA dropped BUS CLEARED VH dropped R2 Address field R1 Data field 3 16 IBM 3745 Models 130 150 160 170 and 17A Hardware Maintenance Reference ...

Page 109: ...l Store Value BUS CLEARED equiva lent to VH R2 contents If Read 5 ð 1 Data Parity DBð B Reg 6 DB1 PV IOH Data Data VH LSAR The CCU waits for VH MDOR to sample data on DBð and DB1 MIOH If PV is raised the parity has to be checked by the CCU If PV is not raised the CCU generates the parity TD dropped 5 VH dropped IO dropped 5 BUS cleared 5 IRR dropped VH TD 5 ADAPTER DESELECTION Interrupt Request if...

Page 110: ...MMAND DATA byte 1 PV Insignificant Scan Int PIO Write Halfword Adapter IO OUT IRR VH TA TD IOC DATA BUS ADDRESS DATA byte ð IOC DATA BUS COMMAND DATA byte 1 PV Scan Int Note Line explanation is given starting on page 3 7 3 18 IBM 3745 Models 130 150 160 170 and 17A Hardware Maintenance Reference ...

Page 111: ...s A selected LA provides the storage addresses at which the data bytes are to be stored For this purpose a pointer is shared by all LAs cycle steal control word CSCW This information is first placed in the adapter registers by the control program using the IOH IOHI instructions in PIO mode A selected channel adapter uses its dedicated pointer which was first loaded by the control program Chapter 3...

Page 112: ...ny interrupt requests The objective is to clear DBð DB1 for any interrupt request IRR from all adapters VH dropped BUS CLEARED CSG 5 Adapters are cabled in priority order and the requesting adapter with the highest priority keeps the Grant Example 6 Adapter No 1 request 6 Adapter 2 Request Adapter 3 Request CSG is chained and only adapter 2 proceeds with the request See Table 2 CSR of the selected...

Page 113: ...ity correct Yes No HALT 5 6 B register contains CSCW ððð ðð ð 2 34 67 8 A B E F 6 CA ð 6 LA 1 6 1 only byte 1 in this control Type of operation word is valid ð both bytes of this control 6 word are valid Pointer LS register number only for CA If LA pointer register contains the address bytes X ð and 1 which are loaded to SAR CSG dropped VH dropped See Tables 3 1 and 3 2 Table 2 Chapter 3 Buses 3 2...

Page 114: ...Write mode see Read mode see Table 4 Table 5 Table 3 1 AIO Operation Sequence for LA Storage Address Transfer CCU IOC ADAPTERS STORAGE ADDRESS TRANSFER PV VH TD 5 Address byte X TD dropped VH dropped VH TD 5 Address bytes ð 1 6 6 VH dropped S A R X ð 1 INCREMENTER 6 Main storage For data transfer in For data transfer in Write mode see Read mode see Table 4 Table 5 Table 3 2 3 22 IBM 3745 Models 13...

Page 115: ... 5 5 Data Data DB1 ð 1 VH TD dropped VH dropped LAST DATA TRANSFER Last byte or last halfword Yes No 5 6 TD 5 M VB EOC B Reg Cycle Steal DBð 5 5 Data Data DB1 TD dropped BUS CLEARED M dropped EOC dropped VB dropped IO dropped ADAPTER DESELECTION VH IRR dropped TD 5 Interrupt Request if any Cycle Steal Request if any Table 4 Chapter 3 Buses 3 23 ...

Page 116: ...ALT 5 TD dropped Last byte or last halfword Yes No 5 LAST DATA TRANSFER 6 TD 5 halfword PV PV M VB EOC Cycle Steal DBð Data Data DB1 TD 5 BUS CLEARED If bad parity HALT 5 M dropped EOC dropped VB dropped TD dropped IO dropped ADAPTER DESELECTION VH IRR dropped TD 5 Interrupt Request if any Cycle Steal Request if any Table 5 3 24 IBM 3745 Models 130 150 160 170 and 17A Hardware Maintenance Referenc...

Page 117: ...e Transfer IO OUT IRR VH CSR CSG TD IOC DATA BUS CSCW D A T A byte ð IOC DATA BUS CSCW D A T A byte 1 EOC PV Note The last data byte is in bytes 0 and 1 same data in bytes 0 and 1 during the inbound operation VB M tag Chapter 3 Buses 3 25 ...

Page 118: ... OUT IRR VH CSR CSG TD IOC DATA BUS CSCW D A T A byte ð IOC DATA BUS CSCW D A T X byte 1 PV EOC VB M Note The last data byte is in byte 0 during the outbound operation VB M tag 3 26 IBM 3745 Models 130 150 160 170 and 17A Hardware Maintenance Reference ...

Page 119: ...ad 16 Byte Transfer IO OUT IRR VH CSR CSG TD IOC DATA CSCW ptr1 ptr2 D A T A BUS byte ð IOC DATA CSCW ptr1 ptr2 D A T A BUS byte 1 EOC PV Note The last data byte is in byte 1 during the read operation VB M tag Chapter 3 Buses 3 27 ...

Page 120: ...TA CSCW ptr1 ptr2 D A T A BUS byte ð IOC DATA CSCW ptr1 ptr2 D A T A BUS byte 1 EOC PV AIO TRA Read Direct Operation 2 Byte Transfer IO OUT IRR VH CSR CSG TD IOC DATAð CSCW D A T A IOC DATA1 CSCW D A T A EOC 3 28 IBM 3745 Models 130 150 160 170 and 17A Hardware Maintenance Reference ...

Page 121: ...ition Q4 One BPC1 is required in positions R4 and T4 if no CSP is installed 3745 Model 150 One BPC1 is required in position T4 if no CSP is installed 3745 Models 170 and 17A If TPS one BPC1 is required in positions A4 and E4 instead of a CAL card CSC CSP cards If no TRA is installed If no CSC is installed in position Q4 No BPC1 or BPC2 installed If a CSC is installed in position Q4 One BPC1 is req...

Page 122: ...ch is attached to IOC and DMA buses The CBC is connected to the IOC and DMA buses from the 3745 basic board 3745 Model 17A 3746 9ðð DMA Bus Y JK Basic Board CBC AB Z IOC Bus Figure 3 7 3746 Model 900 Attachment to 3745 3 30 IBM 3745 Models 130 150 160 170 and 17A Hardware Maintenance Reference ...

Page 123: ...he position of the adapter in the adapter group on the IOC bus Physical Address Wiring The logical address sent on the IOC bus at TA time is compared by each adapter with its proper physical address The type address part is provided by the logic of the adapter card The slot and the adapter group part the bit of lowest weight are imbedded in the printed circuit of the board The adapter group part t...

Page 124: ...ng convention Byte 0 bit 2 is equal to 1 to select a CA indicated by byte 0 bits 4 to 6 Byte 0 bits 4 and 5 is the group address 0 0 CA Group 1 0 1 CA Group 2 Byte 0 bit 6 is the slot address 0 Slot 1 1 Slot 2 Note In case of TPS the B interface uses the slots of the following CA part of the same CA group The address of the CA replaced by the B interface is lost IOC bus at TA time IOC bus at TD ti...

Page 125: ...ð ð ð 1 ð ð ð ð6 ð ð ð ð 1 ð ð ð ð 1 1 1 ð ð ð ð 1 ð ð 1 ð7 ð ð ð ð 1 ð ð ð ð 1 1 1 ð ð ð ð 1 ð 1 ð ð8 ð ð ð ð 1 ð ð ð ð 1 1 1 ð ð ð ð 1 ð 1 1 MOSS Screen CA Address Display As an example address 0800 for CA 5A displayed on the MOSS screen is composed as follows ð 8 ð ð v xxxx ðððx Byte ð at TD Time Bits 4 5 GG ðð and Bit 6 S ð v ðððð 1xxx Byte ð at TA Time Bit ð U ð and Bits 1 4 Type Address ððð1...

Page 126: ... 0 0 1 0 0 and 0 1 1 0 are recognized by the line adapters Type address 0 1 1 0 has the meaning of command broadcast to all LAs Bits 2 and 3 also have a meaning for the slot identification Bits 2 3 01 indicates slot 1 in a group address of the IOC bus Bits 2 3 10 indicates slot 2 in a group address of the IOC bus Bits 2 3 11 broadcast to all LAs Byte 0 bits 5 7 is the group address The group addre...

Page 127: ... ð G G G ð3 ð ð ð 1 ð ð ð 1 11 ð4 ð ð 1 ð ð ð ð 1 21 ð9 ð ð ð 1 ð ð 1 ð 12 1ð ð ð 1 ð ð ð 1 ð 22 11 ð ð ð 1 ð ð 1 1 13 12 ð ð 1 ð ð ð 1 1 23 MOSS Screen LA Address Display As an example address 12 for LA 9 dis played on the MOSS screen is composed as follows 1 2 v ððð1 ðð1ð Byte ð at TA Time Bit ð U ð Bits 2 3 SS ð1 and Bits 5 7 GGG ð1ð Chapter 3 Buses 3 35 ...

Page 128: ...te 0 bit 0 is the IOC connection 0 IOC1 1 IOC2 Byte 0 bits 1 2 11 instruction for 3746 900 Byte 0 bits 3 7 indicates the adapter address IOC bus at TA time Byte ð Byte 1 5 5 ð 1 2 3 4 5 6 7 ð 1 2 3 4 5 6 7 U A A L L L L L C C C C M ð ð I 6 6 ð Output 1 Input Adapter Command Address ð IOH 1 MIOH 11 3746 9ðð ð IOC1 3 36 IBM 3745 Models 130 150 160 170 and 17A Hardware Maintenance Reference ...

Page 129: ...RC ð 1 1 ð ð 1 ð 1 65 ð7G A1 P PRC ð 1 1 ð ð 1 1 ð 66 ð7E A1 D PRC ð 1 1 ð ð 1 1 1 67 ð7E A1 F PRC ð 1 1 ð 1 ð ð ð 68 ð7E A1 H PRC ð 1 1 ð 1 ð ð 1 69 ð7E A1 K PRC ð 1 1 ð 1 ð 1 ð 6A ð7E A1 M PRC ð 1 1 ð 1 ð 1 1 6B ð7E A1 P PRC ð 1 1 ð 1 1 ð ð 6C ð7N A1 E CBC1 ð 1 1 1 1 1 1 ð 7E For more details on 3746 900 see 3746 Model 900 Hardware Maintenance Refer ence online documentation Chapter 3 Buses 3 37...

Page 130: ... Not used 7 Must be set to the OFF position Switch Position for LIB1 3 Type LICs 1 4 Board Switch Location 1 2 3 4 5 ð1M A1 1 ð ð ð ð ð1M A2 ð ð ð ð ð ð1L A2 ð ð ð 1 ð Switch Position for LIB2 Type LICs 5 6 Board Switch Location 1 2 3 4 5 6 7 ð1L A1 1 1 ð ð ð ð ð ð1L A2 ð 1 ð ð ð ð ð Figure 3 8 LIC Board Addressing Switch Position 3 38 IBM 3745 Models 130 150 160 170 and 17A Hardware Maintenance R...

Page 131: ... 1 The floating LIC board 01L A2 is LIB1 type LICs type 1 4 Possibility of 96 lines LICs type 1 4 and 16 lines LICs type 5 6 numbered as follows 32 8ð LIC 1 4 LIC 5 6 ð1M A1 ð1L A1 63 95 ðð 128 LIC 1 4 LIC 1 4 ð1M A2 ð1L A2 31 159 2 The floating LIC board 01L A2 is LIB2 type LICs type 5 6 Possibility of 64 lines LICs type 1 4 and 32 lines LICs type 5 6 numbered as follows 32 8ð LIC 1 4 LIC 5 6 ð1M...

Page 132: ...art 1 or 2 10 Third LIC in part 1 or 2 11 Fourth LIC in part 1 or 2 Byte 1 bits 5 6 indicates the port of the LIC 00 First port 01 Second port 10 Third port 11 Fourth port LIC Type 1 and LIC Type 4A have four ports LIC type 3 and LIC type 4B have only one port Byte 1 bit 7 indicates the transmit or receive address When bit 7 1 receive address When bit 7 0 transmit address LIC Position 1 2 3 4 5 6 ...

Page 133: ...1 ð ð ð 18 12 ð ð ð 1 1 ð ð 1 19 13 ð ð ð 1 1 ð 1 ð 1A 13 ð ð ð 1 1 ð 1 1 1B 14 ð ð ð 1 1 1 ð ð 1C 14 ð ð ð 1 1 1 ð 1 1D 15 ð ð ð 1 1 1 1 ð 1E 15 ð ð ð 1 1 1 1 1 1F 16 ð ð 1 ð ð ð ð ð 2ð 16 ð ð 1 ð ð ð ð 1 21 17 ð ð 1 ð ð ð 1 ð 22 17 ð ð 1 ð ð ð 1 1 23 18 ð ð 1 ð ð 1 ð ð 24 18 ð ð 1 ð ð 1 ð 1 25 19 ð ð 1 ð ð 1 1 ð 26 19 ð ð 1 ð ð 1 1 1 27 2ð ð ð 1 ð 1 ð ð ð 28 2ð ð ð 1 ð 1 ð ð 1 29 21 ð ð 1 ð 1 ð ...

Page 134: ...rd in the LIC unit Byte 1 bits 3 5 indicates the LIC position in the LIC board 000 LIC position 1 001 LIC position 2 010 LIC position 3 011 LIC position 4 100 LIC position 5 101 LIC position 6 110 LIC position 7 111 LIC position 8 Byte 1 bit 6 indicates the port of the LIC 0 First port 1 Second port LIC type 5 has two ports LIC type 6 has only one port Byte 1 bit 7 indicates the transmit or receiv...

Page 135: ... ð11 1ðð 1ð1 11ð 111 Lower Board E ð Upper Board E 1 Port Position for LIC Type 6 at 56 kbps LIC Position LIC Position 1 2 3 4 5 6 7 8 1 2 3 4 5 6 7 8 S 64 68 72 76 S 8ð 84 88 92 M P ð M P ð U U X X A B LLL ððð ð1ð 1ðð 11ð LLL ððð ð1ð 1ðð 11ð Lower Board E ð Upper Board E 1 The LIC cassette can be plugged in an odd position only For plugging restrictions refer to LIC Type 6 Plugging Limitations on...

Page 136: ...1 19 77 ð ð ð 1 1 ð 1 ð 1A 77 ð ð ð 1 1 ð 1 1 1B 78 ð ð ð 1 1 1 ð ð 1C 78 ð ð ð 1 1 1 ð 1 1D 79 ð ð ð 1 1 1 1 ð 1E 79 ð ð ð 1 1 1 1 1 1F 8ð ð ð 1 ð ð ð ð ð 2ð 8ð ð ð 1 ð ð ð ð 1 21 81 ð ð 1 ð ð ð 1 ð 22 81 ð ð 1 ð ð ð 1 1 23 82 ð ð 1 ð ð 1 ð ð 24 82 ð ð 1 ð ð 1 ð 1 25 83 ð ð 1 ð ð 1 1 ð 26 83 ð ð 1 ð ð 1 1 1 27 84 ð ð 1 ð 1 ð ð ð 28 84 ð ð 1 ð 1 ð ð 1 29 85 ð ð 1 ð 1 ð 1 ð 2A 85 ð ð 1 ð 1 ð 1 1 2B...

Page 137: ... Address Position 3 Port 1 1ð28 ð1Q Cð J2 Port 2 1ð29 ð1Q Cð J1 4 Port 1 1ð3ð ð1Q Dð J2 Port 2 1ð31 ð1Q Dð J1 ESS Line Addressing Up to two lines can be addressed for each ESS Byte 1 bit 6 selects the port 0 port 1 1 port 2 Line numbers 1060 through 1063 are dedicated for ESS use Adapter Line Tailgate Number Address Position 3 Port 1 1ð6ð ð1Q Cð J2 Port 2 1ð61 ð1Q Cð J1 4 Port 1 1ð62 ð1Q Dð J2 Por...

Page 138: ...a TIC is addressed Bit 5 0 indicates a command to a TIC Bit 5 1 indicates a command to a TRM Byte 1 bit 6 is the slot address 0 Slot 1 1 Slot 2 IOC bus at TA time IOC bus at TD time Byte ð Byte 1 Byte ð Byte 1 5 5 5 5 ð 1 2 3 4 5 6 7 ð 1 2 3 4 5 6 7 ð 1 2 3 4 5 6 7 ð 1 2 3 4 5 6 7 U A A A A B B B C C C C M T S I D D D D D D D D D D D D D D D D Command R W Data bits Group TRM1 2 Type address TRM TI...

Page 139: ...s IOC bus at TA time Byte ð Byte 1 5 5 ð 1 2 3 4 5 6 7 ð 1 2 3 4 5 6 7 TRM TIC U A A A A B B B C C C C M T S I 1 1 ð 1 ð ð 1 ð ð ð ð ð ð ð 2 ð 1 ð ð 1 ð ð ð ð 1 ð ð 2 3 ð 1 ð ð 1 ð ð ð ð ð ð 1 4 ð 1 ð ð 1 ð ð ð ð 1 ð 1 Line numbers 1088 and 1091 are dedicated for TRSS use Adapter Line Tailgate Number TIC Address Position 1 1 1ð88 ð1Q Að J2 2 1ð89 ð1Q Að J1 2 1 1ð9ð ð1Q Bð J2 2 1ð91 ð1Q Bð J1 Note ...

Page 140: ...hain For Channel Adapters The bypass mechanism is under MOSS and NCP control through the CDF at IPL time or by a shut down command The MOSS tells the CAs what the adapter configuration is on the bus each CA must know if the preceding and the next adapter are present or not Two chains are involved is this mechanism Cycle Steal Grant CSG Autoselection chain 3 48 IBM 3745 Models 130 150 160 170 and 1...

Page 141: ...A12 LA11 LA1ð LAð9 LAð4 LAð3 sample out bypass sample out wrap dot With TPS and HPTSS ESS BOARD ð1G A1 T CA ð7 CA ð5 T CSG bypass CSG L CSG H B D F H J K L M N P Q R S T U V B C C C B C C C T T T C C C C C S C S P P A A A P A A A I I R S S S S S e S e U C D L D C D L D C C M C C C C P e P e C 1 R R 1 R R sa mple LA12 LA11 LA1ð LAð9 LAð4 LAð3 sample out bypass sample out wrap dot Can be FESH or EAC...

Page 142: ... CA is TPS CA01 in the drawing the next CA must be replaced by a BPC card to propagate the CSG through line Autoselection Scenario for CAs As an answer to level 3 interrupts from any CA the CCU issues an IOH X 0F to the bus There is always one CA initially selected in the chain This IOH start the propagation of the sample line from the initially selected CA as follows INPUT The first CA on the bus...

Page 143: ...line BPC Card Installation Rules Model 170 Channels adapters One BPC1 card is required in positions A2 and E2 for TPS Line adapters If no TRA is installed If no CSC is installed in position Q2 No BPC1 or BPC2 are required If a CSC is installed in position Q2 One BPC1 is required in positions R2 and T2 if no CSC or CSP are installed in these positions If a TRA is installed One BPC1 is required in t...

Page 144: ...rs If no TRA is installed No BPC1 or BPC2 are required If a TRA is installed One BPC1 is required in position Q2 One BPC1 is required in positions R2 and T2 if no CSP is installed One BPC2 is required in position P2 If two TRAs are installed One BPC1 is required in position Q2 One BPC1 is required in position R2 and T2 if no CSP is installed Cycle Steal Grant CSG for Model 150 BOARD ð1G A1 CSG H T...

Page 145: ... the routine by calling routine WA01 DIAG WA01 2 Put in the ADP field the IOC bus number 1 on which scoping is planned IOC adapter bus 1 ADP 1 3 Put the adapter number in the LINE field LINE 3 for adapter 03 4 The screen should look like this DIAG WA01 ADP 1 LINE 3 OPT N 5 Then press SEND A check is made to see if the selected IOC bus can be used checking of bits enable present available concurren...

Page 146: ...other MIOH with the selected adapter ENTER Rooccdddd THEN PRESS SEND This allows to perform a write followed by a read operation because inputs may be different 2 oo 02 The requested MIOH is executed and loops on this MIOH until an error is found The error is reported only once via a RAC To continue G for go has to be typed the routine then loops indefinitely until the Power On Reset key is presse...

Page 147: ... the CCU This level 1 is then tested at CCU level and a message LEVEL 1 INTRPT IS RESET is displayed 4 cc 11 Special for the TSS HPTSS and ESS used with option 04 only requests to the selected adapter to set the level 1 interrupt to the CCU This level 1 is then tested at CCU level and a message LEVEL 1 INTRPT IS SET is displayed 5 cc 20 Special for the TSS HPTSS and ESS used with option 04 only re...

Page 148: ...ring write 01 operation 0003 Error during read 02 operation 0004 Error during first write 02 requested Error Bit ERR The error bit patternsdisplayed with the RAC have the following meanings For RACs 231 to 238 Byte 0 Bit 0 CA to CCU level 1 Bit 1 CA to CCU level 3 Bit 2 CA to MOSS level 1 Bit 3 CA to MOSS level 4 Bit 4 TSS HPTSS or ESS to CCU level 1 Bit 5 TSS HPTSS or ESS to CCU level 2 Bit 6 Not...

Page 149: ...For RACs 241 to 244 ERR bits Data received from the adapter Chapter 3 Buses 3 57 ...

Page 150: ... Adapter or Token Ring Adapter CA 05 or TRA 1 Options 02 or 03 Command 02 read Data AAAA Oscilloscope Sync IO line Calibration 0 5 µs IO cycle option 2 40 ms IO cycle option 3 13 ms IO 3 µs 5 3V ðV TA time TD time 1 5 µs ð 5 µs 5 5 3V ðV Byte ð 1 not Bytes ð 1 significant Data bits for CA AAAA For TRA see page 3 46 3 58 IBM 3745 Models 130 150 160 170 and 17A Hardware Maintenance Reference ...

Page 151: ...ms IO cycle option 3 13 ms IO Line 12 µs 5 3V ðV TA time TD time 2 µs 1 µs 5 5 3V ðV Byte ð 1 Bytes ð 1 For LSS HSS Data bits or ELA see AAAA page 3 34 At TA time for LSS ð3 TSS Byte ð bits P 3 and 7 are ON Byte 1 bits 1 and 3 are ON At TA time for HSS ELA ð4 HPTSS ESS Byte ð bits P 2 and 7 are ON Byte 1 bits 1 and 3 are ON Chapter 3 Buses 3 59 ...

Page 152: ...Chaine W31 W11 Data Byte 1 Bit 7 Parity Valid W32 W12 Reset Tag Valid Halfword W33 W13 CA Nohold IRR X22 Xð2 CA MOSS POR CS Req Low CA X23 Xð3 CA Level 1 to MOSS CS Req High CS X24 Xð4 CA Level 4 to MOSS Data Byte ð Bit P X25 Xð5 CA CSG Bypass Data Byte ð Bit ð X26 Xð6 CA CSG Bypass Data Byte ð Bit 1 X27 Xð7 CA Valid Feed Auto Data Byte ð Bit 2 X28 Xð8 Ground Data Byte ð Bit 3 X29 Xð9 CA Valid Fee...

Page 153: ...l Storage 4 15 CSP External Registers 4 15 CCU CSP Register Use 4 18 Ping Pong Buffers 4 18 Processor Characteristics 4 18 Error Management 4 18 Scanner States 4 19 Scanner Commands 4 21 Scanner Status After the IML 4 21 Front End Scanner FES 4 23 Throughput 4 23 Data Flow 4 23 Storages 4 24 FESL Reset 4 25 FESL Reset Flow 4 25 Power ON Reset 4 25 Programmed Reset 4 26 Front End Scanner Adapter FE...

Page 154: ...bps 4 48 RTS Through DCE or Data Paths 4 48 LIC Modem In Process for Non X 21 Lines 4 48 LIC Modem In Process for X 21 Lines 4 48 Internal Clock Function ICF 4 50 LIC Wraps 4 51 Hot Plugging of LICs 4 53 LIC Types 5 and 6 DTE Function 4 54 Transmit Receive Data Mechanism 4 54 LIC Reset 4 54 Line Enable Disable 4 55 Selective Scanning 4 55 LIC Swap 4 55 LIC Address Register Contents 4 55 LIC Contro...

Page 155: ...ations 4 85 Host Support 4 86 DDS Loop 4 87 Alarm Tone Detection 4 87 DSU CSU Configuration 4 88 Portable Keypad Display PKD 4 88 Manual Tests 4 91 PT2 3 4 91 Problem Determination Aid for LIC Types 1 to 4 4 92 Intermittent Error Messages or Messages Lost 4 92 Wrap Tests Controlled from the Host 4 93 Wrap Tests Controlled from the MOSS 4 94 Problem Determination Aid for LIC Type 5 and LIC Type 6 4...

Page 156: ...The TSS in 3745 Models 130 150 160 and 170 Data Flow 4 4 IBM 3745 Models 130 150 160 170 and 17A Hardware Maintenance Reference ...

Page 157: ...Flow Figure 4 1 The TSS in 3745 Model 17A Data Flow For model 17A DMA and IOC buses are connected to the CBC in the 3746 900 This MLA card links the MOSS to the Service Processor through a LAN Chapter 4 Transmission Subsystem TSS 4 5 ...

Page 158: ...s IOC bus LSS Serial link LIC unit Transmission interface However it is possible to connect any LIC board to any low speed scanner LSS by simply moving the serial link cables LSS 1 LIB LSS 2 LIB IOC bus LSS X Transmission interface LSS 6 4 6 IBM 3745 Models 130 150 160 170 and 17A Hardware Maintenance Reference ...

Page 159: ...the ROS code Interconnects the IOC buses through the receivers and drivers Front End Scanner Low Speed FESL The front end scanner low speed FESL provides logical connection between the CSP and the LIC unit It is composed of The front end scanner FES The front end scanner adapter FESA FES It is composed of two layers The front end layer serializes and deserializes the characters provides line servi...

Page 160: ...rd MUX Double Multiplexer Card DMUX DMUX is associated with LIC1s to LIC4s on LIB1 It provides two serial link attachments to connect to two scanner units Each of them Converts the serial link bit stream in a suitable form for LIC buses Performs the serial link clock recovery synchronization and repowering Manages LIC control and clocking The first MUX can attach up to 8 LICs to one scanner if the...

Page 161: ... in a suitable form for LIC buses Performs the serial link clock recovery synchronisation and repowering Manages LIC control and clocking Provides 1 MHz clock signal to the LIC type 5 and LIC type 6 Provides a 4 bit transmit level bus to the LIC type 5 DCEs Line Interface Coupler LIC One line interface coupler LIC attaches up to four FDX HDX lines to the controller Two main families of LICs are av...

Page 162: ... Up to 19 200 bps Not allowed Not allowed Not allowed Not allowed Direct attach ment Note 3 Up to 19 200 bps Not allowed Up to 245 760 bps Up to 9600 bps From 19 200 to 245 760 bps Notes 1 The total number of LICs per CSC is not limited by performance considerations refer to Selective Scanning on page 4 45 for description 2 Called internal clock on CDF information screen 3 Direct attachment allowe...

Page 163: ...ted to a scanner must be less than or equal to 100 The maximum number of LIC positions supported per low speed scanner depends on the line with the highest transmission speed connected to the scanner and is limited to Eight LIC1s to LIC4s per scanner LIB1 or Four LIC1s to LIC4s per scanner LIB3 on model 150 only or Sixteen LIC type 5 or LIC type 6 per scanner LIB2 For each speed LIC types 1 4A 5 h...

Page 164: ...Cs are not scanned if all the lines connected to them are inactive and hence do not load the scanner LIC Internal Clock Function ICF Implemented on each LIC 1 to 4 the internal clock function ICF provides the clock control to Non clocked DCEs Direct attached terminals Line Protocol LIC Types 1 4A 5 LIC Types 3 4B 6 Number of LIC 1 4A or Number of LIC 5 Pairs per LSS 4 4 SDLC FDX 1920 1536 2560 SDL...

Page 165: ...ts the link protocols translates characters and controls the communication interface C Stores the microcode the transmitted received data the line interface parameters and the diagnos tics D Provides registers in local storage for current CSP operation and permanent code in the ROS to start the microcode IPL E Controls the storage and manages by hardware only the cycle steal with the FESL F Contro...

Page 166: ...4 14 IBM 3745 Models 130 150 160 170 and 17A Hardware Maintenance Reference ...

Page 167: ... detects and corrects the single or double bit errors soft or hard of that module When an unrecoverable double error is detected register X 03 bit 1 is set ON a hardstop condition is raised and two data bytes with parity are sent to the CCU The control storage is used to store The scanner microcode The buffers for the transmitted and received data and the line control blocks and parameters Tables ...

Page 168: ...xtended interrupt request 11 Not used 12 Interrupt request line interface address 13 Asynchronous access RAM A B C 14 Data in out 15 Asynchronous access RAM A B C 16 Asynchronous operation status 17 FESL general command 18 Not used 19 PCI IO interrupt level request 1A Current CSP interrupt 1B Address compare control 1C Address compare byte 0 1D Address compare byte 1 1E CSP interrupt masks 1F Loca...

Page 169: ...Chapter 4 Transmission Subsystem TSS 4 17 ...

Page 170: ...r clocks are generated in the CSP A 100 ms clock used for timer purposes A 15 4 µs clock used to refresh the storage Error Management Internal CSP errors detected by the CSP hardware cause a CSP hardstop Two bytes of status informa tion are presented by the CSP either to the CCU control program NCP or to the MOSS after the hardstop condition is detected Hardstop A hardstop condition is handled by ...

Page 171: ...rative The scanner is inoperative when it is not in any other state Initialized The scanner is initialized when the CSP is loaded with the microcode and the FESL storage is initialized to all zeros There is no operation with the control program Connected The scanner is connected when it runs under control of the control program Errors on CCU I O instructions are reported to the control program and...

Page 172: ...ocode execution at address 0 initiating the following functions General reset with a reset of the CSP storage Start of ROS diagnostics Reset of clocks Reset of external registers X 03 CSP error and X 08 error indicators bad parity generator 3 Disables the IOC bus and reset the FESL by setting ON the reset adapter The LICs and ICFs are reset at the same time Programmed Reset The control program can...

Page 173: ...rs just IMLed are in the last two bytes of the mailbox These values must be displayed before any mailbox exchange between the CCU storage and the corresponding scanner for example CCU functions Below are the possible statuses of the scanner after an IML Current State Possible Scanner Commands Resulting State Connected Stop Reset Dump IML Disconnected stop Reset Reset Initialized Disconnected go St...

Page 174: ...heck X C9ðF MUX address different between CDF and values from the scanner X C91ð FES internal error X C92ð MUX error X C94ð FES failing to answer X C98ð AIO error X C9Fð Bypass bit different between CDF and values from the scanner Figure 4 2 Values of the Last Two Bytes of the Mailboxes after IML 4 22 IBM 3745 Models 130 150 160 170 and 17A Hardware Maintenance Reference ...

Page 175: ... all the throughput is devoted to that LIC Data Flow As shown on the next data flow the FES A Controls the FES timing the exchange with the CSP and the RAM operation B Controls the transfer of characters between the front end and the CSP C Handles the data halfwords coming from or going to the control storage D Provides cycle steal control for the CSP E Interrupts the CSP on level 2 for buffer and...

Page 176: ...r bit service RAM C for line service These RAMs are used in receive and transmit and give a total of 4x64 256 halfwords per RAM The FES storages can be displayed or altered from the operator console using the TSS functions 4 24 IBM 3745 Models 130 150 160 170 and 17A Hardware Maintenance Reference ...

Page 177: ...SA latches Serial link 6 to MUX Power ON Reset The FES reset line signal is driven by CSP R 04 bit 2 This bit is set by the hardware in case of POR or by the microcode in case of programmed reset It is reset by the microcode This FES reset signal 1 Resets the FES latches and sets the FESA reset tag 2 Disables the lines between the CSP and the FES 3 Resets the FES RAMs all bits are set to zero and ...

Page 178: ...crocode by setting bits 0 1 and 2 of the control register common address X A with line address 00 Bit 0 resets FESA latches and sets FESA serial link to no transmission Bit 1 resets FESA RAMs Bit 2 freezes FESA 4 26 IBM 3745 Models 130 150 160 170 and 17A Hardware Maintenance Reference ...

Page 179: ...the serial link bit stream and con versely FESA Data Flow The FESA data flow shows The interconnection of FESA with the two serial link processors inbound and outbound The FESA to FES interconnection The internal organization around the FESA RAMs to manage the data and control information exchanged by the FES and the serial link Chapter 4 Transmission Subsystem TSS 4 27 ...

Page 180: ...e RAM as a working area to serialize and assemble the data bursts Each RAM is divided into 32 areas one area per line In the control RAMs each area contains the line register information The RAMs are time shared by the FES and the two serial link interconnections inbound and outbound The FESA synchronizes the various RAM requests It monitors the FES RAM access requests and moni tors the outbound a...

Page 181: ...bles show the bits of registers X 13 and X 15 used to access the FESA inbound and outbound RAMs X 13 Line Interface Address X 15 Asynchronous Operation Command Local Store 6 CHHITMIO Input FESA Inbound Outbound RAM Layout FESA control register bit 5 controls the type of opera tion OFF Write or output operation ON Read or input operation Bits Functions 0 0 Not used always 00 x x x Card address x x ...

Page 182: ...trol Xmit interrupt stack 0 1 0 1 0 FESA MUX LIC registers See note FESA MUX LIC registers See note 0 1 0 1 1 Not used FES diag Not used FES diag 0 1 1 0 0 DSR RI parameters DSR RI work timer 0 1 1 0 1 RLSD parameters RFS TI drop w rlsd 0 1 1 1 0 ICF RAM 4C ICF RAM 4C 0 1 1 1 1 Not used FES diag Not used FES diag Bit Decoding E I Z R R Write FESA ctrl reg bit 5 0 Outbound RAM Read FESA ctrl reg bi...

Page 183: ...enabled information sent by the LICs over the inbound serial link Note Disabled LICs are seen as not present by the FES and consequently these LICs are not scanned in order to accept higher throughput on remaining actives lines The LIC 0 present is not given to the FES which always assumes that the first LIC is present as a minimum configuration The FESA makes no difference between the LIC s physi...

Page 184: ...he changes of any of these signals by using specific timers DSR RI and RLSD are confirmed for both raising and falling edges Integration of I X 21 is performed for I drop only I going ON is immediately reported to FES in any case A different timer starts each time the associated signal switches The change is confirmed when the time out is reached The confirmation delay is specified for each signal...

Page 185: ...ce saved in the inbound control RAM TI remembrance is reset by the microcode Confirmation of Clear X 21 The 16 bit time confirmation of the X 21 steady states is performed in the LIC The only X 21 steady state confirmed by the FESA is clear when the protocol requires a 10 ms confirmation instead of the 16 bit time Modem out The modem out pattern coming from the FES is stored by the FESA in the out...

Page 186: ...nk From scanner to LIC This information is carried in a frame structure Frames A frame is a sequence of 32 double slots data control data control data control data control double slot ð double slot 1 double slot 31 5 5 5 A superframe is defined as a sequence of 32 frames A corresponding delimiter is put in control slots of frame 31 to signal the end of a superframe frame ð frame 1 frame 31 Slots A...

Page 187: ...into the LICs bit stream On the serial link side the DMUX Monitors the frames coming from the FESA Retrieves and decodes the serial link bit stream encoded information code Manchester Detects the frame sync and transmits it to the LICs Copies in the proper register the incoming information addressed to the DMUX On the LIC bus side the DMUX Monitors the serial information coming from the LICs Trans...

Page 188: ...rs serial cable 6 6 6 6 6 Frame superframe 1 or 2 Sync 2 5 Driver 5 Rcve 2 Serial bus Frame inbound 8 interconnection Xmit 2 Frame outbound 1 5 5 Driver 5 6 Physical address 4 Line frame configuration 2 MUX registers EC number 2 LICs reset registers 5 LICs reset 8 Hardware reset 5 Drivers 5 5 Or Power ON reset 5 To from FESA To from LICs Note Numbers in parentheses are the number of leads 4 36 IBM...

Page 189: ...SC MUX ð to 3 CSC MUX ð to 3 Cable 1 Cable 1 DMUX Reset The DMUX card and consequently the two MUXs can be reset POR Serial Serial link 1 link 2 x x x Analog reset Reset Serial link Serial link MUX 1 2 control 1 control 2 ex SL ctl Reset Serial link both MUXs 2 present 6 5 Reset LICs 5 Reset LICs Reset LICs 6666 6666 6666 xxxx xxxx 1234 5678 1 A POR line coming from the power supply one line for t...

Page 190: ...through the serial link by selecting the appropriate bit in the LIC reset register of the MUX The reset allows to isolate the LIC from the MUX via the LIC bus and from the attached lines DMUX Hot Plugging Bottom connectors with several level of indentations and an analogic power ON reset delay provide the required power sequences 4 38 IBM 3745 Models 130 150 160 170 and 17A Hardware Maintenance Re...

Page 191: ... LICs Loads the information devoted to the SMUX into the proper register On the LIC bus side Monitors the serial information coming from the LICs Transmits it to the FESA after Manchester encoding Sends the control information from the SMUX registers to the FESA In addition the SMUX provides A bit timing synchronized from the received data PLO function Two functional clock signals to the LICs sync...

Page 192: ...the previous SMUX switch settings or use the following table to determine the maximum authorized transmit level in your country Country non switched lines Transmit level Country non switched lines Transmit level AG and A PG generally 0 Greece 0 Australia 13 Hong Kong 9 Canada 0 Iceland 10 Chile 6 Ireland 0 Denmark 10 Italy 10 EMEA generally 6 Japan 15 Finland 10 Sweden 10 France 15 UK 13 SMUX Data...

Page 193: ...nbound 8 interconnection Xmit 2 Frame outbound 1 5 5 Driver 5 6 Physical address 4 Line frame configuration 2 MUX registers EC number 2 LICs reset registers 5 LICs reset 8 Hardware reset 5 Drivers 5 5 Or Power ON reset 5 To from FESA To from LICs Note Numbers in parentheses are the number of leads Chapter 4 Transmission Subsystem TSS 4 41 ...

Page 194: ...g ways By the POR line coming from the power supply The POR line acts on both SMUX A and B cards Both SMUX A and B are reset and send a LIC reset to each associated LICs By an analog reset when a SMUX card is hot plugged When absence of signal is detected on the outbound serial link LIC Reset LIC reset is done either by the selective reset line coming from the SMUX or by an analog reset circuit wh...

Page 195: ...require internally generated clock signals for either Low speed DCE attachment Direct attachment to terminals The internal clock function ICF on the LIC card itself provides these clock facili ties Interface Lines DMUX buses DTE to DCE interfaces Power ON reset Modem out lines 5 5 LIC reset 5 5 Modem ln lines ICF clocks 3 5 Transmitted data LIC clocks 3 5 5 Received data Other clocks 5 LIC DCE rec...

Page 196: ...eive mode LIC Reset See also DMUX Reset on page 4 37 The purpose of the LIC reset command is to isolate the LIC from the LIC bus and from the attached lines DMUX card provides one reset lead per LIC At power ON all leads are activated during the power ON reset until the DMUX detects a start pattern from the FESA After power ON one reset lead may be activated on request to reset the logic in the co...

Page 197: ... logical address 7 it occupies the slots assigned to LIC number 7 and is seen as LIC in physical position 7 by the FESA and FES If this LIC has no line enabled it will not be scanned See LIC Enabled Leads on page 4 31 for the microcode handling of these leads Selective Scanning Selective scanning gives more flexibility for backup configurations using the same scanner as only the LICs which have at...

Page 198: ...s Physical addresses 2 3 4 7 Configuration DMUX LIC LIC LIC LIC 12 lines at 1 2 kbps 2 card C D E H 4 lines at 9 6 kbps Physical addresses ð 2 3 6 7 Configuration DMUX LIC LIC LIC LIC LIC 1 line at 64 kbps 3 card A C D G H 8 lines at 9 6 kbps 8 lines at 1 2 kbp Physical addresses 1 Configuration DMUX LIC 1 line at 256 kbps 4 card B LIC Swap The logical addressing function implemented in the 3745 L...

Page 199: ...2 LIC logical address bit 2 2 LIC wired address bit 2 3 Enable disable logical add 3 Not used 4 Not used 4 EC number 5 Not used 5 EC number LIC Control Register The LIC control register X 02 bit 1 and bit 3 Line enable E0 and E1 controls the swapping Bits Meaning 0 High speed line 1 Line enable E0 2 X 21 CCITT used by FESA 80 3 Line enable E1 4 Not used 5 Transmit bit echo Enable Clock Mode Regist...

Page 200: ...ng to the value of modem out bit 5 the lead RTS of the DCE interface will change with the new modem out register or at the boundary of transmit data burst as follows RTS through the DCE path When modem out bit 5 is ON RTS changes according to the modem out bit 1 sent to the LIC by the FESA in even frames RTS change occurs as soon as the new modem out is loaded RTS through the data path When modem ...

Page 201: ...confirmation instead of a 16 bits time In that case the LIC sends modem in to the FESA and the FESA itself confirms the state for DCE clear after a 10 ms count state confirm still being delivered after a 16 bits time for the other three states Chapter 4 Transmission Subsystem TSS 4 49 ...

Page 202: ... direct attached terminals use their own clock The LICs and their direct attached unclocked terminals The ICF is not used when a LIC is attached to a clocked DCE Depending on the above configurations the ICF mode can be Internal 3745 or External and the clockings are provided as follows Internal Mode The internal clocking mode is set by the microcode at initialization time in the LIC card ICF acti...

Page 203: ...CF since the DCE provides the transmit and receive clocks to both the LIC and itself LIC Wraps Refer to Problem Determination Aid for LIC Types 1 to 4 on page 4 92 for more infor mation on wraps Advanced Operations Guide SA33 0097 to invoke these function from the MOSS console Diagnostic Descriptions SY33 2059 for diagnostics using LIC wraps Two LIC wraps are available on the CCITT interface of th...

Page 204: ...llowing wraps LIC logic wrap Drivers Control OFF C X 5 I Transmit data OFF DCE Xmit data X 5 Rcve data Loop 3 on V 24 Loop 3 on the V 24 interface performs the following wraps LIC logic wrap Drivers DTR DTR X 5 DSR RTS RTS X 5 DCE RFS Xmit data X 5 Rcve data Only DTR and RTS are wrapped to DSR and RFS before the drivers Loop 3 on X 21 Loop 3 on the X 21 interface performs the following wrap LIC lo...

Page 205: ... card has three levels of indentation to provide the required power sequences When plugged power ON the LIC logic gets into the reset state long enough to avoid transient disturbances on the interfaces Chapter 4 Transmission Subsystem TSS 4 53 ...

Page 206: ...r differ according to the type of line LIC DTE High speed Low speed Telephone FES SMUX serializer serializer DCE Manchester In outbound seserializer deserializer line encoded Serial link A 5 data bits plus 1 delimiter The data is passed from to the FES to the telecommunication line via the MUX and LIC as shown above The LIC communicates with the FES to Request new data to be transmitted when in tr...

Page 207: ...dress bit 1 2 LIC logical address bit 2 2 LIC wired address bit 2 3 Enable disable logical add 3 Odd position 4 Not used 4 EC number 5 Not used 5 EC number LIC Control Register The LIC control register X 02 bit 1 and bit 3 line enable E0 and E1 controls the swapping Bits Meaning 0 Not used 1 Line enable E0 2 Not used 3 Line enable E1 4 Not used 5 Transmit bit echo LIC Wraps Refer to Problem Determ...

Page 208: ...ype 6 A 700 Ω load is maintained on the line during loop 3 Loop 3 is started by test control TC rise The DCE answers back by rising test indicator TI then starts data looping LICs Hot Plugging LIC card bottom connector have three levels of indentation to provide the required power sequences When plugged power ON the LIC logic gets into the reset state for a time long enough to avoid transient dist...

Page 209: ... Problem Determination Aid for LIC Type 5 and LIC Type 6 on page 4 95 and appropriate 786X and 5822 documentation listed in the MIP bibli ography Data Flow LIC5 Telephone line DCE SMUX DTE Control panel Telephone line DCE Logic Part DTE serializer deserializer DCE microprocessor and signal processor DCE ROS RAM and NVPROM Analog Part DCE coder decoder DCE transmit receive filters DCE line transfor...

Page 210: ... LIC type 5 The speed setting cannot be done either by NetView or by MOSS Configurations LIC type 5 DCEs are compatible with IBM 586X and 786X DCEs They operate in point to point or multipoint configurations as follows Point to Point LIC Type 5 to LIC Type 5 3745 3745 LIC5 LIC5 Primary Primary Point to Point LIC Type 5 to 586X or 786X 3745 LIC5 DCE DTE Primary Primary or Secondary 4 58 IBM 3745 Mo...

Page 211: ...ary Secondary 1 Transmit clock received 2 Transmit clock external Speed control DTE Multipoint LIC Type 5 to LICs Type 5 3745 3745 LIC5 o LIC5 Control Tributary 3745 LIC5 Tributary Multipoint LIC Type 5 to 586Xs 3745 LIC5 o DCE DTE Tributary Control o DCE DTE Tributary Chapter 4 Transmission Subsystem TSS 4 59 ...

Page 212: ...586Xs Including Tailed This configuration does not support LPDA2 Tailing Tailed 3745 LIC5 o DCE DCE o DCE DTE 1 2 1 Control Tributary Control Tributary DCE DTE DCE DTE 1 1 Tributary Tributary 1 Transmit clock received 2 Transmit clock external Speed control DTE Configuration Options Depending on the IBM native or CCITT type of modulation the different ways of setting the various CNM functions are ...

Page 213: ...and Modulation LICs type 5 use combined amplitude and bi phase differential modulation encoding Each couple phase amplitude corresponds to a single bit pattern In addition the data is scrambled descrambled to avoid single frequencies over the telephone line when repetitive data patterns appear at the DCE interface Below are the Modulation rate Carrier frequency Number of encoded bits per signaling...

Page 214: ... QAM V 33 QAM V 33 RTS RFS Delay 2 ms 2 ms C and D Native Mode Speed 9600 bps 7200 bps Modulation Rate 2400 2400 Carrier Frequency 1700 Hz 1700 Hz Number of encoded bits per signal ling periods 4 3 Modulation QAM or QAM with TCM QAM or QAM with TCM RTS RFS Delay 2 ms 2 ms E CCITT Mode Speed 9600 bps 7200 bps 4800 bps Modulation Rate 2400 2400 2400 Carrier Frequency 1700 Hz 1700 Hz 1700 Hz Number o...

Page 215: ...ential encoding RTS RFS Delay 2 ms 2 ms DCE to Telephone Line Interface LIC type 5 interfaces the telephone line through balanced impedances matching the networks both input and output circuitries may be regarded as 2 port networks Unbalanced 5 Transmit o source terminator 6ðð Ω balanced output stage o Unbalanced Receive o receiver terminator 6ðð Ω balanced input stage o The circuits are not damag...

Page 216: ...ns former secondary windings limit the maximum peak voltage to 12 V line to ground Transit Time The transit time is the time that elapses between the input of a bit in the local trans mitter and the output of this bit from the remote receiver assuming a zero trans mission delay over the telephone line Modulation type Transit time ms 14 400 12 400 9600 7200 4800 2400 IBM Native 21 4 21 4 17 2 18 0 ...

Page 217: ...is ON green LED 2 lit Severe local DCE error is detected yellow LED 1 and 2 flashing LIC card plugged in a wrong place Line Specifications 4 wire non switched lines US and Canada non conditioned Other countries CCITT M 1020 or M 1025 conditioning Line Spectrum V 27 bis Centered on 1800 Hz Spreads from 1000 to 2600 Hz Native and V 29 Centered on 1700 Hz Spreads from 450 to 3050 Hz including a 12 5 ...

Page 218: ... µs from 600 to 2600 Hz Less than 3000 µs from 500 to 2800 Hz Insertion loss at 800 Hz 13 dB 4 Harmonic distortion 25 dB minimum below received level Phase jitter No more than 15 peak to peak normally 10 Frequency shift 5 Hz Signal to noise ratio 24 dB Impulse noise Threshold of 8 dB to signal level at an average rate of 18 impulses per 15 mn M 1025 Line Characteristics Attenuation distortion Over...

Page 219: ...rmation these lines should have the following specifications Attenuation distortion Overall loss relative to that at 800 Hz over carrier section 3 8 to 13 0 dB from 300 to 400 Hz 3 8 to 5 8 dB from 400 to 600 Hz 3 8 to 3 8 dB from 600 to 2400 Hz 3 8 to 9 4 dB from 2400 to 3000 Hz 3 8 to 17 4 dB from 3000 to 3400 Hz Delay distortion Group delay relative to the minimum group delay Less than 1750 µs ...

Page 220: ...n TI is raised CD and RFS are dropped at the local and the remote interface and the DATA traffic through the DCE is interrupted Read and set by customer i Set by CE only Options Settable in the Local LIC Type 5 Settable in the Remote LIC Type 5 if not CCITT PKD LPDA 2 PKD LPDA 2 DCE address Default speed Point to point Multipoint Control Tributary Type IBM native Long training sequence Anti stream...

Page 221: ...uality threshold From 0 to 15 displayed in hexadecimal 0 to F LPDA 2 setting ranges from 0 to E Control panel setting ranges from 0 to F F means no threshold If the line quality parameter is above or equal to that threshold the line quality indication LQ in the background information blinks on the displayed value and the buzzer gives an audible alarm At installation the threshold value is 8 which ...

Page 222: ...vel One digit from 0 to 3 wired on the LIC5 card that specifies the level of the electronic components Microcode EC level The EC level of the ROS and UVPROMs can be read on the PKD from the ROS themselves They cannot be updated Host Support Host support for LIC type 5 is NetView from R3 using LPDA 2 functions See LPDA Description SY33 2064 for LPDA 2 protocols formats and commands Three sets of co...

Page 223: ...than 50 ms Set TC ON Detect TI ON in less than 700 ms Set RTS ON Detect RFS ON in less than 200 ms Send data to be looped on TD 2 End loop Stop data transmission Put RTS OFF Detect RFS OFF in less than 50 ms Put TC OFF Detect TI OFF in less than 100 ms Self test The self test from OFFline diagnostics pre empts any other DCE func tions It can be run only when the DCE is not connected to the network...

Page 224: ...Remote power OFF tones Remote failure tones Alarm tones are not detected if the DCE is executing a self test If a failure tone and a power OFF tone are detected while executing a local status only one of them is displayed Tone Characteristics Frequency 325 Hz 10 Hz Level As written in NVRAM default value provided by the switches on the SMUX card Power OFF tone duration 100 ms 20 ms if power OFF la...

Page 225: ... or 586X configuration local or remote is achieved by keying a set of commands from the IBM 5869 PKD connected to the relevant LIC type 5 See the MIP SY33 2070 for detailed command procedures Chapter 4 Transmission Subsystem TSS 4 73 ...

Page 226: ...D CONFIG LOC ð 1 2 3 TEST STATUS FULL CONFIG REM 4 5 6 7 ANALOG DIGITAL BCKUP CMD 8 9 A B PD LOC LOOP C D E F GO ERASE EXIT STOP the following are the available main display operations For procedures display analysis and actions refer to 3745 Problem Determination Guide SA33 0096 3745 Connection and Integration Guide SA33 0141 4 74 IBM 3745 Models 130 150 160 170 and 17A Hardware Maintenance Refer...

Page 227: ...F full B backup Notes 1 WRAP is displayed instead of line address and line quality if a manual loop back test is running Transitions between 0 and 1 on the screen indicate that activity is taking place on the lead except for RD and TD If there is no activity the actual status is displayed 2 When CD 0 RD indicates the speed of last data reception When RFS 0 TD indicates the speed of last data trans...

Page 228: ...n 2 Execution 3 Report Command Rejection In some cases commands are rejected No response The remote did not answer disruption of data transmission has already taken place Bad response The remote gave an invalid answer wrong FCS disruption of data has already taken place Busy TC ON If the lead TC is ON all operator commands are rejected with the following message BUSY TC ON The buzzer sounds one be...

Page 229: ... and transitions Analog Test This test key 8 provides line analysis It involves both local and remote DCEs and lasts 6 s on each side Digital Test This test key 9 is a transmit receive test It involves both the local and remote DCEs Blocks of data are sent from the local to the remote DTE which wraps them back to the local one Block errors are counted on both sides and displayed on both screens Se...

Page 230: ... not changed Update the configuration all fields may be updated Address a specific DCE via its serial number Long timer 10 mn for LLAP Contact sense operate remote only All the above commands are reset at Power OFF DCE re initialization Buzzer Control Each time a valid key is pressed there is a short bip The absence of bip means that the key is either irrelevant to the current protocol or has not ...

Page 231: ...ne is detected If end of configuration has not been received the message stays on the screen during 5 mn This message appears as soon as the PKD is present if the con dition still holds CONFIG MISMATCH Configuration error KEY n STUCK When the indicated key appears to be pressed during more than 5 s The message stays 10 s then the control panel is reinitialized This indicates a mechanical or electr...

Page 232: ... communication through private limited dis tance lines The data is encoded and decoded as for DDS protocols rules and so on Note The LIC type 6 offers no local area data channel LADC attachment facility Maintenance Approach Same as LIC type 5 see page 4 57 Data Flow LIC6 DDS or DCE LD line SMUX DTE Control panel Logic part DTE serializer deserializer DCE microprocessor and signal converter DCE ROS...

Page 233: ...he LIC type 6 card 19 2ðð 96ðð 56 ððð 6 6 O In V 35 like mode 56 000 bps only one speed is available In V 24 like mode 19 200 and 9600 bps two speeds are available and must also be set at installation time from the PKD The speed setting cannot be changed either by NetView or by the MOSS Configurations LIC type 6 DSU CSUs are compatible with IBM 5822 10 DSU CSUs They operate in Point to point and m...

Page 234: ...it o terminator 135 Ω balanced output stage o Unbalanced receiver Receive o terminator 135 Ω balanced input stage o The circuits are not damaged under the following conditions Open circuit Short circuit between the leads Short circuit from either lead to ground The DC isolation between input and output leads with regard to ground is greater than 20 MΩ Surge Protection Primary protection A line sur...

Page 235: ...ssuming a zero trans mission delay over the telephone line Transmitter and receiver refer to the V 24 interface Transmission Speed bps 56 000 19 200 9600 Transit time ms 35 33 33 RFS Delay The RFS delay is 7 to 20 bit time for LIC type 6 in any configuration It must be added to the transit time to evaluate the turnaround time 9600 bps 2 5 ms 19 200 bps 1 5 ms 56 000 bps 0 5 ms Chapter 4 Transmissi...

Page 236: ...auge of the wires Lengths and Gauges The next table gives the maximum lengths in km and miles for the most common gauges used Table 4 1 Maximum line length according to wire diameter and transmission speed Transmission Speed Wire Diameter in mm Gauge 0 4 26 0 5 24 0 6 22 0 8 20 56 000 bps 4 2 km 2 6 miles 6 0 km 3 7 miles 8 1 km 5 0 miles 13 7 km 8 5 miles 19 200 bps 5 8 km 3 6 miles 7 9 km 4 9 mi...

Page 237: ...se the group delay distortion Options and Configurations The LIC type 6 is not configurable via LPDA 2 commands The speed option V 35 V 24 is set from a switch on each LIC type 6 card but the speed option 19 200 9600 is set from the PKD See Speed Setting on page 4 81 The options are set in a non volatile PROM except for microcode and machine EC level The next table shows the options available to b...

Page 238: ...ince LPDA 2 commands flow into the LIC type 6 as other pieces of data the disable option may be selected if there is a chance that the LPDA 2 header may be erroneously detected in the data bit stream The LPDA 2 header is guaranteed unique for the following data transmission protocols SDLC NRZI BSC USACII or EBCDIC ALC DCE address Control and primary LIC type 5 always 01 Tributary and secondary LIC...

Page 239: ...k data from DDS 6 Detect end of bipolar code violation and current polarity reversal 7 Drop TI and reset the modem busy bit The test lasts as long as a code violation or polarity reversal is detected It runs only if the LIC type 6 is in operate mode Alarm Tone Detection A failure signal is sent when a hard internal failure is detected provided that network services are enabled This signal contains...

Page 240: ...RD activity also indicates speed of reception F high B low Notes 1 WRAP is displayed instead of DSU CSU address and line quality if a local manual loop back test is running 2 Transitions between 0 and 1 on the screen indicate that activity is taking place on the lead If there is no activity the actual status is displayed DSU CSU Information When the background information is displayed the operator...

Page 241: ...available 2 DDS LOOP ACTIVE brings a command rejection Digital Test See page 4 99 Local Loop Back This command prepares the DCE for a loop 3 test See page 4 96 Speed Change Only for 19 200 9600 bps See Speed Settings page 4 81 Configuration The PKD being connected to a given LIC type 6 the local DSU CSU configuration settings may be Scrolled and displayed Updated Some fields are read only for exam...

Page 242: ...ent if CD is still 0 KEY n STUCK When the indicated key appears to be pressed during more than 5 s The message stays 10 s then the operator panel is reinitialized This indicates a mechanical or electrical problem aa LIC6 FAILED At power ON the initial self test failed DEFAULT CONFIG Operator intervention is required to reconfigure the DSU CSU INV PATTERN RCV Invalid pattern received ex a DDS patte...

Page 243: ... analysis procedures LLAP yes ñ Run continuously until keying EXIT Descriptions of the above manual tests are given later in this chapter under Problem Determination Aid for LIC type 5 and LIC type 6 PT2 3 A 10 pin connector is available on the LIC type 6 panel to connect a PT2 3 used to investigate and record control and data signals Chapter 4 Transmission Subsystem TSS 4 91 ...

Page 244: ...races external internal SIT traces checkpoint trace NCP line trace TSS dump Port swap refer to Advanced Operations Guide SA33 0097 Note Internal SIT trace and TSS dumps can be transferred via RSF to be ana lyzed remotely by the PST CE Intermittent Error Messages or Messages Lost Intermittent error messages or messages lost without alarm or BER created may come from an intermittent hardware failure...

Page 245: ...ry DCEs Local Remote Tailing Tailed DCE DCE DCE DCE Note 2 Note 2 Cable Cluster Local Remote DCE DCE Terminal oo oo 5 Local loop back V 54 loop3 5 Remote loop back v 54 loop2 5 Link level 2 5 OLTT or IBM SNA test 5 Remote loop back on secondary link Stand alone for LIC type 1 to LIC type 4 Integrated for LIC type 5 and LIC type 6 Notes 1 The primary DCE is equipped with the data multiplexing featu...

Page 246: ... LIC type 1 to LIC type 4 Integrated for LIC type 5 and LIC type 6 Notes 1 A line position can be plugged with a line cable with a wrap plug LIC type 1 2 4 or with a wrap cable LIC type 3 When the TSS diagnostics are run the hardware for a selected line is Tested up to the LIC drivers Fully tested if a wrap plug or a wrap cable is present on the selected line Plugging a wrap plug or wrap cable sel...

Page 247: ... lead wrap command takes place LIC line analysis procedures LLAP See the Advanced Operations Guide and the Problem Determination Guide for details Manual Tests Controlled from the PKD To test the DCE part of the LIC type 5 and LIC type 6 all the following tests are manually initiated from the PKD Notes 1 The above tests run continuously until keying EXIT See the Connection and Integration Guide fo...

Page 248: ...onsibility to send data under RFS control and check receive data when CD is ON Local Self Test for LIC Type 5 5 DCE Line wrap block A line wrap block may be plugged into the line interface to allow line interface checking If the line wrap block is not plugged when local self test is selected from the PKD a remote power loss indication may appear at the remote DCE During the test execution TI is ra...

Page 249: ...transferred from the RAM in the NVRAM 2 The indication is recorded for a future LPDA 2 report if applicable 3 The LIC type 6 is put in idle mode 4 A warning is displayed Remote Self Test Supervisory message 5 5 DCE DCE Self test Local Supervisory message Remote A supervisory message is sent from the local DCE to the remote along with the DCE address On reception of this message the addressed DCE s...

Page 250: ...n is received within 5 s maximum and displayed at local DCE in the following sequence Remote line status current quality number of hits within the last 15 mn warnings logged current receive level Remote DTE interface state and transition since the last request During execution TI is raised RFS and CD dropped at the local and remote DTE interfaces and the data traffic through the DCE is interrupted...

Page 251: ... into line analysis report The other parameters are measured during the test itself Data driven parameters Received level RL Minimum received level last 15 mn MRL Number of impulse hits HIT Number of line breaks LBK Larger than 10 dB below average value for a duration longer than 10 ms typical values Impairments measured during test Line round trip delay RTD Measured at local side is the differenc...

Page 252: ...ransmitted data activity on both DCEs Received line signal quality Note Devices beyond the remote DCE such as tailed DCEs and lines are not tested Detailed LLAP procedures are described in the Problem Determination Guide TSS Interface Cables For details on interface cables and connectors see the External Cable References SY33 2075 4 100 IBM 3745 Models 130 150 160 170 and 17A Hardware Maintenance ...

Page 253: ...14 Reset FESH 5 15 Transmit Operation 5 15 Microcode Functions 5 15 FESH Hardware Functions 5 15 Receive Operation 5 17 Microcode Functions 5 17 FESH Hardware Functions 5 17 Modem Interface Management 5 19 Modem In Management 5 19 Modem Out Management 5 20 Modem Retrain 5 21 Time Out Values 5 22 Customization Parameters 5 22 Error Detection and Reporting 5 23 Program Hardware Checks 5 23 Hardware ...

Page 254: ...Prefix Validity Checking in Receive 5 37 Problem Isolation and Network Management 5 38 External Wrap Facility 5 38 Communication Interfaces 5 40 FESH DCE Interface 5 40 Cable Diagrams 5 41 Clocking 5 42 Local Attachment 5 42 5 2 IBM 3745 Models 130 150 160 170 and 17A Hardware Maintenance Reference ...

Page 255: ...The HPTSS in 3745 Models 130 150 160 and 170 Data Flow Chapter 5 High Performance Transmission Subsystem HPTSS 5 3 ...

Page 256: ...The HPTSS 3745 Model 17A Data Flow For model 17A DMA and IOC buses are connected to the CBC in the 3746 900 This MLA card links the MOSS to the Service Processor through a LAN 5 4 IBM 3745 Models 130 150 160 170 and 17A Hardware Maintenance Reference ...

Page 257: ...ock speed up to 2 048 Mbps The HSSs can also be directly connected back to back without a network When directly attached to each other the adapters can operate at any one of the three speeds set by the NCP 245 76 kbps 1 47456 Mbps or 1 8432 Mbps The connection to a 3725 is limited to 245 76 kbps The HSS provides two separate V 35 or X 21 interfaces to a network However only one V 35 or X 21 interf...

Page 258: ...wo lines associated with a particular HSS are addressed by the TD1 field of the IOH TD1 bit 6 selects one of the two lines TD1 bit 7 selects either the transmit or the receive interface of the line TD1 bit 7 0 selects the transmit interface the TD1 bit 7 1 selects the receive interface Line Scanner Line Board Tailgate Adapter and Line Address Card and Position Port Connector Number Position 3 Port...

Page 259: ...diate F1 Dump Control blocks no status F4 Dump Control blocks status F5 The following MOSS command is supported by the HSS Commands Codes Hex Wrap 2E Interface Types Two types of line interface are available at the exit of the FESH card Refer to Communication Interfaces on page 5 40 for more details 1 V 35 2 X 21 leased including French Transfix They allow the 3745 to be connected to U S T1 type l...

Page 260: ...nterfaces V 35 and X 21 called X 21 Transfix in France leased line SDLC HDLC duplex protocol on point to point leased line A network adapter may be required such as DCE or network communication terminal equipment NCTE Echo suppression Frame up to 64 kbytes long SNA maximum size CSP ROS common with other microcode load modules SDLC address compare performed by FESH NCP buffer prefixes automatically...

Page 261: ...smit frames is done in a FESH buffer instead of CSP storage SDLC transmit continue command not supported SDLC receive monitor command not supported No multiplexing only one line HSS microcode deals with buffer prefixes only with scanner interface trace SIT The remaining buffer prefix handling is done by the FESH CCU storage access for NCP buffer data is done through DMA instead of IOC cycle steals...

Page 262: ...er Issues SDLC transmit continue or receive monitor commands Uses data areas but NCP buffer pointers for both transmit and receive operations FESH to CSP The physical interconnection between the FESH and the CSP is identical to that of the internal intercon nection between the FES fonction and the CSP of the LSS For board and card locations refer to the Maintenance Information Procedures manual SY...

Page 263: ...t Start data management FESH to DMA Bus This connection is used for direct CCU storage access and specifically NCP buffer prefix exchange Data transfer between the high speed line and main storage Parameters and status exchange between the NCP and the HSS microcode Communication Scanner Processor CSP The HSS CSP hardware is identical to that of the LSS CSP Refer to the Chapter Transmission Sub sys...

Page 264: ... t e r To DMA n Layer 5 a DMA l Receive Layers Bus B u s Receive Receive Receive Receive RAM Byte Bit Front Front Data 5 Layer Layer End End Buffer Queue Figure 5 4 Transmit and Receive Layers Transmit Layers The transmit layers are composed of The front end circuits which perform the following functions Serialization of data Flag generation Zero insertion CRC generation The transmit bit layer whi...

Page 265: ...SH RAM Receive byte layer Handles NCP buffer prefixes for receive Interconnects with CSP layer external registers and control words Handles chaining thru NCP buffers for SDLC receives Handles chaining thru NCP buffers for frame relay frame receives Also use the SNAP header format table to determine the offset and maximum counts to use for the first two buffers in the receive chain for frame relay ...

Page 266: ...sters and cycle steal operations Handles the protocols of CSP external registers and cycle steal operations Handles cycle steal requests from transmit receive data management modem in out layers on a priority basis Scanner Status After the IML At the end of scanner IML it is possible to get from the CCU storage the status of the scanners associ ated with their mailbox The 16 byte mailboxes are loc...

Page 267: ...he DMA bus Builds the transmit control word CW to be sent to the FESH Indicates to the FESH transmit layer external register setting the Transmission coding mode NRZI or non NRZI at set mode Start of transmit initial Start of transmit Stop of transmit operation hard and soft FESH Hardware Functions Transmit Initial Command The transmit initial command is used between the CSP and FESH hard ware to ...

Page 268: ... byte layer machine operations are overlapped so that the transmission of data can continue while data is being obtained from the CCU via the DMA interconnection This overlap of operations continues until a zero buffer pointer is detected When a zero buffer pointer is detected the bit layer instructs the front end to send the CRC and ending flag followed by the ending sequence specified at set mod...

Page 269: ...mand Stop of receive operation command Flush command FESH Hardware Functions Receive Command When the FESH is enabled it always Monitors for flag flush other characters Performs address compare On flag recognition starts accumulating received characters in the receive queue buffer Performs zero deletion Performs CRC accumulation The two CRC characters are not stored in the receive queue buffer On ...

Page 270: ...ESH continues receiving characters from the line Raises an interrupt to the CSP and indicates to the microcode that a new buffer pool is needed Waits for start receive continue from the microcode On reception of start receive continue from the microcode the hardware resumes the normal process Flush End of Frame Command When receiving I frames to be flushed a frame reject frame FRMR can be received...

Page 271: ...ead State Confirmation On V 35 lines the FESH is capable of monitoring Data set ready DSR Clear to send CTS However in normal operation the CSP microcode only monitors the DSR and CTS leads The FESH modem in layer starts a count before delivering the new modem in value to the CSP in order to avoid unwanted interrupts caused by modem in leads bouncing or specific DCE behavior The confirmation delay...

Page 272: ...steady states which are detected by the FESH hardware I R Clear OFF ð Controlled Not Ready CNR OFF ð 1 16 bit time Controlled Ready CR OFF 1 Ready for Data RD ON X don t care Local Wrap LW OFF X ðF data received 16 bit time Remote Wrap RW OFF X 33 data received 16 bit time To confirm any state the hardware verifies that the state remains unchanged during a count of 16 bit times When a state is con...

Page 273: ...to the CCU is SCF bit 3 1 modem check LCS X E2 CTS dropped If CTS does not recover but there is no transmission in progress the error will be detected and reported on the next transmit command as SCF bit 3 1 modem check LCS X F2 CTS failed to come up 5 Data reception is not affected X 21 Modem Retrain On X 21 lines modem retrain is entered when a DCE uncontrolled not ready or DCE controlled not re...

Page 274: ... 2 s 40 s 25 2 s Customization Parameters Using the CDF Display Update option 1 at the MOSS console the CE or the customer can have access to the HSS parameters The CE or the customer can choose two parameters the DMA size see note 3 hereunder and the DSR integration timer The DMA size see note 3 hereunder is a function of the number of HSS line adapters installed A DMA size of 64 is correct for o...

Page 275: ...ed during I O operations on the IOC bus These errors may be detected by the CCU or by the HSS Errors are related to CCU storage and address checks invalid sequences and timed out IOH IOHI instructions 2 HSS problems Invalid interrupts Microcode detected program failures These set the microcode check bit in the error status and cause the NCP to issue a get microcode check instruction CCU level 2 in...

Page 276: ...DMA internal error DMA logical error DMA storage protect address exception DMA interconnection error in read or write a DMA parity check b Notes 1 The following errors can occur concurrently a and b 2 All the above listed errors are reported to the NCP via a level 2 interrupt and associated status area as an LCS and ELCS code Refer to Line Communication Status LCS on page 5 31 and Extended Line Co...

Page 277: ...tion of the timer is in the range of 100 ms to cover a complete transfer operation on the DMA bus DMA Burst Count Checker This checker verifies that the transfer is satisfactorily completed on the DMA bus when the burst count in the FESH reaches zero Chapter 5 High Performance Transmission Subsystem HPTSS 5 25 ...

Page 278: ...check Checkers 6 SCTL FESH Card Card 5 5 5 3 Error Lines Reporting Reporting DMA errors is done by issuing a level 2 interrupt to the CSP The nature of the error is set into an LCS ELCS Refer to Line Communication Status LCS on page 5 31 and Extended Line Communication Status ELCS Initial Status B 110 for HSS on page 5 35 for code description When any of the above checkers becomes active 1 The har...

Page 279: ...parity error or because the external reg ister does not exist in the FESH the acknowledge signal is not sent to the CSP Also if the data bus parity is incorrect during an external register write the acknowledge signal is not sent to the CSP When acknowledge is not returned to the CSP by the FESH the CSP sets the adapter interconnection check bit ON external register X 03 bit 6 1 and terminates the...

Page 280: ...e checkers becomes active The FESH Stores the corresponding error condition in an error register Interrupts the CSP microcode at level 0 The CSP microcode Stops the transmit and receive operations in process In case of transmit puts the transmit data line at mark In case of receive stops the phase monitor Line Interface Check A driver check function is implemented on the line interfaces of the FES...

Page 281: ...pe x Not used Not used x Not used Line interface address bit ð x Not used Line interface address bit 1 x Not used Line interface See note below address bit 2 x Not used Line interface address bit 3 x Invalid input Line interface IOH address bit 4 x Adapter interconn check Chapter 5 High Performance Transmission Subsystem HPTSS 5 29 ...

Page 282: ...OSS level 1 interrupt Type 3 Internal logical errors detected by the CSP microcode A CCU level 1 or MOSS level 4 interrupt is set Hard Stop A CSP microprocessor check has been encountered The CSP hardware responds with the error status The following tables shows the detailed responses that may be presented to a get error status command Hard Stop Error Status Detected by CSP Hardware Byte ð Bit Mea...

Page 283: ...hen any bit is ON in this byte the service request bit bit 1 in the SCF must be OFF except for modem retrain in NCP BSC Bit Meaning x Modem retrain x Idle detection SDLC or format exception NCP BSC EP BSC x LPDA reply received but TI failed to come up transient error x Data check SDLC NCP BSC EP BSC x Flag off boundary SDLC or bad PAD NCP BSC x In phase EP BSC TI ON NCP BSC SDLC x DLE error NCP BS...

Page 284: ...aracter ð 1 ð Transparent text mode DLE STX are first char ð 1 1 Header mode SOH is first character Special See paragraphe Initial Status B 100 Special on page 5 33 for more explanation ISF FSF F ð 1 2 3 4 5 6 7 Meaning 1 ð ð Special status Errors See paragraphe Initial Status B 110 Internal Box Error on page 5 34 and paragraphe Initial Status B 111 Hardware Error on page 5 36 for more explanation...

Page 285: ...eout nothing received ACR COS DLO or PND failed to drop X 21 timeout on ready for data 1 ð ð ð ð ð 1 x Ending condition on start stop 1 ð ð ð ð 1 ð x X 21 timeout during clear 1 ð ð ð ð 1 1 x 386x 58xx test control active X 21 timeout on proceed to select 1 ð ð ð 1 ð ð x DLE EOT disconnect sequence received 1 ð ð ð 1 ð 1 x Lost data 1 ð ð ð 1 1 ð x Poll entry too long 1 ð ð 1 1 ð ð x EOT transmitt...

Page 286: ...le monitor incoming call or dial if autocall interface Initial Status B 110 Internal Box Error HSS The code is the value of the LCS bits 0 to 7 fields ISF FSF F Code Description C0 AIO error indicates a hardware error during an adapter initiated operation cycle steal C2 Adapter interconnection check indicates a FESH hardware error C4 CSP interconnection error indicates a CSP FESH interconnection h...

Page 287: ...in bus parity check 16 Combination of f and h 18 4 DMA time out on read 1A 2 DMA interconnection error on read 22 d Storage unrecoverable error SCTL internal error 24 Combination of e and f 28 g DMSW parity check on primary secondary bus 2A 5 DMA bus driver fault 34 Combination of e f and g 3A 6 DMA burst count error 44 Combination of 2 e f and g 4A h DMSW driver fault 5A Combination of 1 e f and ...

Page 288: ...ne is enable monitor incoming call or dial if autocall interface Initial Status B 111 Hardware Error HSS The code is the value of the LCS bits 0 to 7 fields ISF FSF F Code Description E2 CTS dropped indicates clear to send failed during transmission EE V 35 DSR dropped X 21 DCE not ready or external clock failure indicates that DSR failed for V 35 connection or that the DCE is not ready for an X 2...

Page 289: ...33 2069 and Advanced Operations Guide manual SA33 0097 1 Alter display 2 CSP address compare 3 CSP dumps These facilities invoked from the operator console help in analyzing modifying the contents of the HSS storage and registers CSP and FESH Programming Support for Problem Determination It includes as for LSS microcode 1 Error detection 2 Error collection 3 Error reporting Types of error tracked ...

Page 290: ...d as specified by the interface ID bit indirect register X 06 bit 1 and the clock defaulted to the clock speed selected by the NCP at set mode during a wrap The external clock is under microcode control as specified by external register X 11 Wrap Mode at DCE Level The wrap is started from the MOSS console The diagnostics can perform a wrap function from the transmit to the receive interface on the...

Page 291: ... cables between the FESH card and the tail gate A wrap plug is required Local NCTE Wrap Test Or Loop Test 3 checks the transmit and receive ability of the 3745 up to the first network communication terminal equipment NCTE Remote NCTE Wrap Test Or Loop Test 4 checks the transmit and receive ability of the 3745 up to the second NCTE and including the communication media VTAM Path Test Or Loop Test 5...

Page 292: ... corresponding bit in the FESH to select the proper port To determine which interface was selected by the hardware V 35 or X 21 on the selected port the micro code reads the cable ID in the FESH The FESH is also capable of supporting different electrical interfaces Each of the two physical interfaces can independently support the following interfaces to the network com munication terminal equipmen...

Page 293: ...5 V 35 DTE Mutually Exclusive The FESH supports the CCITT standard V 35 interface All interface signals conform to the electrical specifications as stated in the various CCITT standards X 21 Interface The HSS supports the 1987 CCITT X 21 standard for transmitting data at speeds up to 2 048 Mbps Cable Diagrams DCE interface signals exit the FESH using two top card connectors one for interface 1 and...

Page 294: ...ropagation delays in the cable the transmit clock received from the DCE or NCTE is re driven and sent to the DCE or NCTE in synchronization with the data Local Attachment The HSS supports direct attachment no DCE with another HSS using the X 21 or V 35 interface When directly connected together one FESH is designated as local attach by the cable ID bits and auto matically provides the receive cloc...

Page 295: ... TIC Bus Interconnection Control 6 14 Receive Operation 6 14 Transmit Operation 6 15 Token Ring Multiplexor TRM Card 6 15 IOC Bus Interconnection 6 16 Summary of the IOC Bus Interface Signal Lines 6 17 TIC Bus Interconnection 6 17 Summary of the TIC Bus Signal Lines 6 18 TRM Arbitration Mechanism 6 18 TRA Resets 6 19 Power ON Reset and Tag Reset 6 19 Programmed Reset 6 19 TIC Reset 6 19 Diagnostic...

Page 296: ...The TRSS in 3745 Models 130 150 160 and 170 Data Flow 6 2 IBM 3745 Models 130 150 160 170 and 17A Hardware Maintenance Reference ...

Page 297: ... Flow Figure 6 1 The TRSS in 3745 Model 17A Data Flow For model 17A DMA and IOC buses are connected to the CBC in the 3746 900 This MLA card links the MOSS to the Service Processor through a LAN Chapter 6 The Token Ring Subsystem 6 3 ...

Page 298: ...s A token ring network can replace switched and non switched telephone lines and also allow voice commu nications over the same cabling system that carries data communications The token ring complies with the recommendation 802 5 of IEEE and the ISO 8802 5 IBM Token Ring Network It is an information transport system that provides high speed 4 Mbps or 16 Mbps connection between users within a singl...

Page 299: ...ber Token Ring Adapter The adapter in the 3745 has the following functions Frame and address recognition Token generation Error checking and logging Buffering transmit and receive Time out controls Connect the product to the token ring network For Example The 3745 is connected to the IBM Token Ring network through the token ring interface coupler card TIC A cable composed of two pairs of copper wi...

Page 300: ...vice to the main ring for its attached lobes Nodes or stations are attached to the lobes The multistation access units that include electronic or electro mechanical switching elements are shown below Figure 6 4 Multistation Access Unit 6 6 IBM 3745 Models 130 150 160 170 and 17A Hardware Maintenance Reference ...

Page 301: ...ecomes a true frame General Frame Format Physical Physical Transmission Data Transmission Header Trailer Data Link Information Control Figure 6 5 Frame Format Once a station is physically attached to a ring it first synchronizes itself to the data patterns passing through it over the ring Token Ring Access Control Protocol Figure 6 6 Token Ring Access Protocol Example Token Ring Encoding The diffe...

Page 302: ...e has its own token ring interface coupler card to gain access to the token ring network or ring The 3745 has up to eight token ring interface coupler cards type 2 TIC2 which can work at 4 or 16 Mbits Bridges A bridge is a high speed switching device that allows linking multiple rings and maintaining a physical ring separation Figure 6 7 Ring to Ring via Bridge Example 1 6 8 IBM 3745 Models 130 15...

Page 303: ...Figure 6 8 Ring to Ring via Bridge Example 2 Typical Multi Floor Wiring Chapter 6 The Token Ring Subsystem 6 9 ...

Page 304: ...TRM is not allowed The combination of all the TRAs in a controller is called the TRSS One token ring network can be accessed by each TIC card Packaging Only one TRA may be installed on the basic board of the Models 00A and 00C and up to two TRAs in the Model 00B Each TRA may control up to two token rings The TRM interconnects with the input output control bus IOC bus and it is accessed from the CC...

Page 305: ... P S C T O 2 2 H H L E E A A C C L L L L A A A A 1 9 4 3 ð 5 5 5 TRSS LSS HSS or ELA Figure 6 11 Basic Board Model 160 A B C D E F G H J K L M N P Q R S T U V W X C C C C C C C C T T T C C C C C N C N P S S A A A A A A A A I I R S S S S S A S A U C T L D L D L D L D C C M C C C C C C C T O R R R R 2 2 L C F C F S E S E P S P S H H C C C C L L L L L L A A A A A A A A A A 8 7 6 5 1 1 1 9 4 3 2 1 ð 5...

Page 306: ...on the data stream that passes through it on the ring 1 Repeat the received data without copying it 2 Repeat and copy the received data 3 Change the state of single bits in the received data before retransmitting it 4 Originate the transmission of data 5 Remove from the ring messages that it has previously transmitted The next figure shows the relationship between the message processor and the oth...

Page 307: ...vel bit and byte protocols on the ring The Message Processor The message processor acts as the master control element for the protocol handler and the TIC bus inter connection control in the TIC card Interaction with these functional areas is across an 18 bit local bus The message processor is the general name for the microprocessor microcode and the hardware It consists of the following items A m...

Page 308: ... coding usable by the adapter By counting received clock pulses the protocol handler assembles the bit stream into halfwords units Parity is generated on the received data de serialized from the ring to check data validity through the adapter During the receive sequence cyclic redundancy check CRC calculation is begun on the received data The destination address is compared against the stored valu...

Page 309: ...th the destination and source addresses When the entire information field has been transferred the protocol handler inserts the CRC characters that have been accumulated in the message The protocol handler begins to remove strip any data from the ring that is being received The incoming data stream is searched for a match of the source address with the address of the TIC After a match is found and...

Page 310: ...gnostic register Level 1 error status register Level 2 error status register MOSS error status register IOC Bus Interconnection The IOC bus interconnection allows communication between the TRAs and the CCU NCP or between the TRAs and the MOSS The IOC bus signal lines go to from the TRM card bottom connector I O pins See Chapter 3 Buses and Switching for more information 6 16 IBM 3745 Models 130 15...

Page 311: ...lect L2SSLOU Adp prev X line out Modifier M TRM X Parity valid PV TRM X X Parities Pð P1 TRM CCU X X X Power on reset POR Power blck Reset RESET Switch TA TA CCU X TD TD CCU X X Valid halfword VH TRM X X X Valid byte VB TRM X Figure 6 14 Summary of the IOC Bus Interconnection Signal Lines TIC Bus Interconnection The TIC bus is a bidirectional bus which connects the TRM card to the TIC cards via th...

Page 312: ...er DTACK TRM TIC X X X acknowledge Bus error BERR TRM X Bus request 2 BR TIC X Bus grant 2 BGR TRM X Bus busy BBSY TIC X Bus release BRLS X Interrupt IR TIC X request 2 Interrupt IACK TRM X acknowledge 2 Reset 2 RESET TRM System clock BCLK TRM X X X System last SLT TIC X Transfer Figure 6 15 Summary of the TIC Bus Signal Lines TRM Arbitration Mechanism Since two TIC cards can be attached to the TR...

Page 313: ...e TIC 1 More generally all other functions and all other registers are forced in their inactive state Programmed Reset The programmed reset is initiated by a PIO IOH or MIOH It allows the program to reset the TRM without resetting the attached TIC s and the connect or disconnect state of the TRM The result is the same as the hardware reset except the TIC reset bits the disconnect mode latch and th...

Page 314: ...detects the halt tag it sets the level 1 status register with the exception of bits 7 and 11 Bits 7 and 11 reflect the status of the indicated latches when the get level 1 error status register PIO is executed During an IOC level 1 interrupt bits 0 3 5 6 8 10 and 12 15 are valid only if bit 4 is ON Bit 0 This bit R W bit is ON if a read PIO AIO is being executed It is OFF if a write PIO AIO is bei...

Page 315: ...ed If the TRM is CCU PIO disabled the level 1 error status register can be successfully read only by an MIOH Bit 12 This bit TRM TIC is ON if an AIO or a get line ID PIO is being executed by the TRM when the halt tag is activated If this bit is ON it means that bits 13 and 14 are valid If this bit is OFF it means that the error cannot be associated with any particular TIC Bits 13 and 14 Bits 13 an...

Page 316: ...connection type 1 0 1 1 TIC interconnection type 2 Internal The TRM is suspected Type 1 The working TIC is suspected Type 2 All TICs can be suspected idle state error This error encoding is performed by the TRM using the checkers in the TRM See Error Detection and Reporting on page 6 20 The status provides two independent error fields 1 PIO MMIO operations which require program retry 2 Operations ...

Page 317: ... set in the register again Line Identification Line ID Generation When the CP receives a level 2 interrupt it places a PIO get line ID command on the IOC bus This command is decoded by all adapters However only one according to the level 2 interrupt priority mechanism will answer with a line ID For adapters set to the same priority the first adapter on the IOC bus will be serviced first The line I...

Page 318: ...nnected all MIOH MMIO errors will be logged in the MOSS error status register If the TRM is disconnected and the associated MOSS control bit is OFF all MMIO and DMA errors for a TIC are logged in the normal level 2 error status register Format 2 is not used for the MOSS error status register TIC Adapter Check Register The adapter check interrupt is generated when the TIC has encountered an unrecov...

Page 319: ...ad write x Illegal OP Illegal OP code detected Parm ð TIC register 13 code Parm 1 TIC register 14 Parm 2 TIC register 15 x Parity Local bus parity error Same as for illegal OP error detected by TIC processor code x Parity Local bus parity error Same as for illegal OP error detected by TIC during code external operation with CCU x Parity Local bus parity error Same as for illegal OP error IOC detec...

Page 320: ...ð 2 are ignored overrun receive operation x Invalid Unrecognized error Parm ð TIC register 13 interrupt interrupt was generated Parm 1 TIC register 14 Parm 2 TIC register 15 x Invalid Unrecognized error Parm ð TIC register 13 error interrupt was generated Parm 1 TIC register 14 interrupt Parm 2 TIC register 15 x Invalid Unrecognized transmit Parm ð TIC register 13 XOP operation request was Parm 1 ...

Page 321: ...that a disconnected cable during the lobe media test will cause a lobe wire fault check to appear in both the display token ring status function and the ring status field field E of the token ring interconnect function Refer to the Problem Determination Guide GA33 0096 When a lobe wire fault is detected the TIC will be frozen and the status will remain unchanged until the next open is issued Using...

Page 322: ...6 28 IBM 3745 Models 130 150 160 170 and 17A Hardware Maintenance Reference ...

Page 323: ...lection Error 7 13 Cycle Steal 7 14 Cycle Steal CS Chain 7 14 Removing a CA from the Cycle Steal Chain 7 14 CA MOSS Connection 7 15 Interrupt Requests 7 16 Level 1 Interrupt Request 7 16 Level 3 Interrupt Request 7 16 Two Processor Switch TPS 7 17 TPS TCS Mode 7 17 Loosely Coupled Host Attachment 7 17 Alternate Path Host Attachment 7 17 Alternate Path Host Operations 7 18 Presentation of Status 7 ...

Page 324: ...The CA in 3745 Models 130 150 160 and 170 Data Flow 7 2 IBM 3745 Models 130 150 160 170 and 17A Hardware Maintenance Reference ...

Page 325: ...ata Flow Figure 7 1 The CA in 3745 Model 17A Data Flow For model 17A DMA and IOC buses are connected to the CBC in the 3746 900 This MLA card links the MOSS to the Service Processor through a LAN Chapter 7 Channel Adapter CA 7 3 ...

Page 326: ...y be mixed in the 3745 The BCCA operates in native mode only under the Network Control Program NCP it does not support the Partitioned Emulation Program PEP The BCCA acts as a CADS when buffer chaining mode is not set except that it does not support ESC mode Note In the following pages specifics of a type 7 CA will be indicated by BCCA CA stands for CADS and BCCA Packaging One CADS or BCCA is pack...

Page 327: ...hen the 3745 is connected to systems 308X or 43XX When a CA defined with the data streaming option is connected to a host which does not support data streaming abend code 300A is issued Non Supported Features The following features are not supported Bus extension Command retry Suppress data interlock transfer Dynamic reconnection Configuration Four channel interfaces are available by means of the ...

Page 328: ...rface B CADR 7B Figure 7 2 CA Configuration with TPS Feature CA 5 Host Interface Main CADR 5 Storage 5 CAL 5 I 5 5 CCU O C CA 6 Host Interface CADR 6 5 5 MOSS CAL 6 Autoselection 5 CA 7 Host Interface CADR 7 5 CAL 7 5 CA 8 Host Interface CADR 8 5 CAL 8 5 Figure 7 3 CA Configuration without TPS Feature 7 6 IBM 3745 Models 130 150 160 170 and 17A Hardware Maintenance Reference ...

Page 329: ... S U C O L R F E R E C A MOSS Auto Sel CADR B H to from B C C O CA U O O S S N C N SEL F T T H T OUT I A R A R I O D O N O Byp F 5 N C A L N L T 5 P E E B T M L M D F 5 R U E D O R F S R U B D WRAP A L U C E L R F E E C B F Fuse only for UK CADRUK Card only Figure 7 4 CA Components and Data Flow Chapter 7 Channel Adapter CA 7 7 ...

Page 330: ...ess Line address decoding is handled entirely by the NCP ESC Mode The ESC mode is supported for byte multiplex channels only and allows the con troller to emulate the 2701 Data Adapter Unit 2702 Transmission Control and 2703 Transmission Control using existing host programs and subchannel addresses This mode requires the Partitioned Emulation Program PEP in the 3745 and a separate subchannel addre...

Page 331: ...l program AIO mode should always be used when performance is critical CA Instructions The CA is controlled by instructions issued from the control program The NCP and PEP exclusively use adapter input output halfword IOH instructions and input output immediate halfword IOHI instructions These instructions examine or set the CA registers load or read buffers and ini tiate cycle stealing Note Throug...

Page 332: ...sed by check or error conditions Level 1 interrupt requests to MOSS are caused by check or error conditions when the MOSS is the owner of the resource IPL Level 3 Interrupt See Level 3 Interrupt Request on page 7 16 Level 3 interrupt requests are caused by 1 Initial selection interrupt requests 2 Data status interrupt requests Level 4 Interrupt Level 4 interrupt requests are raised to MOSS in diag...

Page 333: ... Bus out Command out Data in 1 Data out 1 Disconnect in Operational in Operational out Request in Select in Select out and Hold out Service in Service out Status in Suppress out 1 Used only with High Speed Transfer and Data Streaming options Chapter 7 Channel Adapter CA 7 11 ...

Page 334: ...utoselection AS Chain Valid Feed Auto T T Sample Sample Sample Out Bypass Out Out 5 CA5 5 Card 5 CA7 5 CA8 Sample Sample Sample In In In Sample Bypass T T Sample Out Wrap Dot T T T Terminator Figure 7 5 Example of Autoselection Chain The AS chain allows up to four CAs to be installed without specific jumpering that would be configuration dependent The AS chain carries the following signals Valid F...

Page 335: ...That is polling for the highest priority interrupt starts with the CA following the previously selected CA or the one after that if it is no longer in the AS chain CA 5 follows CA 8 CA 6 follows CA 5 Autoselection Error When the hardware detects a problem on the sample chain no CA will answer at TD time and an IOC bus timeout will be set The control program must determine the failing CA Chapter 7 ...

Page 336: ...t low priority CSG L or CS grant low thru out CSG T or CS grant low bypass out CSG B CSG L 5 T 6 6 6 CSG T Byp CSG T CSG T CA5 5 Card 5 CA7 5 CA8 6 6 6 T T CSG B Byp Bypass T Terminator Figure 7 6 Example of Cycle Steal Chain Removing a CA from the Cycle Steal Chain To avoid potential host system hangup no data transfer must be in progress for the CA which has to be removed from the CS chain The c...

Page 337: ...55555 4 lines 5555555555555 CA ENABLE 5 8 555555555555 4 lines CA INTERFACE ENABLED 5 8 1 line CA HLIR 1 line CA LLIR 1 line CA NOHOLD 5 5 ALL CAs DISABLED to PCC Card Figure 7 7 CA Link to MOSS Note The CA NOHOLD line coming from the MOSS broadcast line is used to validate the CA MOSS POR CA x MOSS RESET and CA x ENABLE lines Chapter 7 Channel Adapter CA 7 15 ...

Page 338: ...uffer chaining outbound is set An initial selection sequence occurs for commands other than Write Write Break TIO ot NO OP when buffer chaining inbound is set NSC status cleared if buffer chaining is not set A system reset sequence occurs ESC TIO status cleared Selective reset Interface disconnect Channel bus out check 2 Data status transfer request End of an inbound data transfer if buffer chaini...

Page 339: ...sely Coupled Host Attachment The term loosely coupled means either 1 Two separate hosts each running its own access method VTAM with each host attached to an interface of a CA with TPS or 2 A single host running different access methods one access method associated with one interface of a CA via a TPS and the other access method associated with the other interface of the same CA When running in a ...

Page 340: ...some error the CA enters this state even though DE is presented to the command The CA remains switched to the same interface and does not return to neutral The host on receiving the UC status issues a sense command to deter mine the cause of the error The CA returns to neutral when receiving a command other than No Op or Test I O Ending statuses to the host are as follows 1 Normal Tagged Status Th...

Page 341: ...the channel When select out is trapped by the non switched interface it raises status in and presents X 10 The host channel responds by dropping hold out or select out and address out thereby disconnecting the interface The host does not issue further commands until a tagged DE status is received This status is presented when the active CA interface returns to the neutral state The CA hardware rai...

Page 342: ...terrupt request is made Selective Reset over Interface with Allegiance When the CA recognizes the selective reset it returns to the neutral state and issues a level 3 initial selection interrupt request No hardware reset occurs except for a tagged DE status caused by a previous busy status on the opposite interface During the initial selection if the opposite channel polls the CA in response to re...

Page 343: ...CA initial L3 interrupt request or a CA data status L3 interrupt request depending on when this condition was detected Also the CA will disconnect from the channel interface when working on the channel If this condition occurred during an initial selection sequence the hardware will set interface disconnect which is accessible by an input X 00 instruction bit 0 1 1 If it occurs during a data statu...

Page 344: ...se two modes resides in the validation of the commands received over the IOC interface Interrupt requests for these two modes are routed to the CCU or MOSS as specified in the definition of command MOSS out X 07 Channel Wrap Possibilities Refer to the MIP for test procedures Internal Wrap A wrap possibility on the CADR card exists which helps the diag nostics in FRU detection This may also be used...

Page 345: ...12 o HOLD OUT OPERATIONAL OUT o 13 o OPERATIONAL OUT Figure 7 8 Tag Wrap Plug Wiring P N 26F1754 Mating Side Bus Wrap Plug P N 26F1755 D o ð2 o B BUS OUT P o ð3 o BUS OUT P BUS OUT ð o ð4 o BUS OUT ð BUS OUT 1 o ð5 o BUS OUT 1 BUS OUT 2 o ð6 o BUS OUT 2 o ð7 o BUS OUT 3 o ð8 o BUS OUT 3 BUS OUT 4 o ð9 o BUS OUT 4 BUS OUT 5 o 1ð o BUS OUT 5 BUS OUT 6 o 11 o BUS OUT 6 BUS OUT 7 o 12 o BUS OUT 7 o 13...

Page 346: ...lay screen appears This screen can also be displayed by selecting the channel interface display CID function from MOSS menu 2 The information displayed is Host attachment information NSC address MOSS enable disable request Interface status enabled disabled The CID screen also allows to modify the enable disable request CA Initialization The CA initialization is performed when a CA receives a POR s...

Page 347: ...itializes each CA Initialization Third Part Chaining Only those CAs that passed the first and second parts of the initialization can be installed in autoselection and cycle steal chains Chaining process is performed during IPL Only when all the CAs are initialized can the control program start Chapter 7 Channel Adapter CA 7 25 ...

Page 348: ...7 26 IBM 3745 Models 130 150 160 170 and 17A Hardware Maintenance Reference ...

Page 349: ... Branch Trace 8 11 Branch Trace Buffer 8 11 Conditional Branch Trace 8 12 Mailbox Description 8 13 Exchange Time Outs 8 13 CCU to MOSS Communication Out Mailbox 8 14 MOSS to CCU Communication In Mailbox 8 14 Mailbox Commands 8 15 LSSD Operation 8 17 Data Flow 8 17 LSSD Testing Circuit 8 17 MOSS Disk Drive Interaction 8 19 Disk Commands 8 19 Read Write Operations 8 20 MOSS Operator Console Connecti...

Page 350: ...The MOSS in 3745 Models 130 150 160 and 170 Data Flow 8 2 IBM 3745 Models 130 150 160 170 and 17A Hardware Maintenance Reference ...

Page 351: ...gure 8 1 The MOSS in 3745 Model 17A Data Flow For model 17A DMA and IOC buses are connected to the CBC in the 3746 900 This MLA card links the MOSS to the Service Processor through a LAN Chapter 8 Maintenance and Operator Subsystem MOSS 8 3 ...

Page 352: ... MOSS processor responds to interrupts from the CCU from its attached adapters LAs CAs and from its own error detection circuits It controls access to the MOSS storage The MOSS processor is packaged on the MPC card Packaging Refer to Figure 8 3 on page 8 6 for MOSS structure on 3745 Models 130 170 and to Figure 8 4 on page 8 7 for MOSS structure on 3745 Model 17A The MOSS board includes A MOSS pro...

Page 353: ...et occurs the led on the top of the MPC card is turned ON The panel displays code 001 a read MMIO bus is started by the MOSS code If the result is good the led is turned OFF and the display code goes to 002 If the result is not good after a two second time out the led starts blinking POR Code Panel 5 PCC 5 MPC 5 MSC 5 MCC 1 5 MAC 2 5 MLA 2 5 DFA 1 On 3745 Models 1xð 2 On 3745 Model 17A Figure 8 2 ...

Page 354: ...LE LOCAL CONSOLE MOSS STORAGE MSC Card ADAPTER OR REMOTE CONSOLE MODEM Card ALTERNATE CONSOLE MCC Card V 22 bis RSF MODEM 24ðð bps DISK FILE Flexible Disk ADAPTER Drive FDD Card Hard Disk Drive DFA Card HDD Figure 8 3 MOSS Structure on 3745 Models 1x0 Note 1 To CAs 05 08 is a control line that allows enabling disabling or resetting the CAs 8 6 IBM 3745 Models 130 150 160 170 and 17A Hardware Maint...

Page 355: ...MOSS 5 To From CCU MOSS PROCESSOR 5 To CAs ð5 ð8 See Note 1 MPC Card 5 ADAPTER CARD MEMORY BUS MAC Card Two Megabyte DISK FILE Flexible Disk MOSS STORAGE Drive FDD MSC Card ADAPTER CARD Hard Disk Drive DFA Card HDD Figure 8 4 MOSS Structure on 3745 Model 17A Note 1 To CAs 05 08 is a control line that allows enabling disabling or resetting the CAs Chapter 8 Maintenance and Operator Subsystem MOSS 8...

Page 356: ...el or the console CCU IPL Line adapter IML 2 Maintain the 3745 with Remote support facility RSF for 3745 Models 1x0 Concurrent diagnostics LIC hot plugging Box event handling error recording analysis and display alert alarm gen eration Line services line wrap tests line interface display token ring interface display ESS interface display CCU control program procedures Machine history files configu...

Page 357: ...efer to the steps of MOSS Changes of State 9 2 MOSS 5 MOSS IML 1ð 5 OFFLINE 2 4 7 Power On 1ð Reset 5 MOSS 5 MOSS 4 5 6 5 DOWN ALONE 1 9 2 3 6 8 Power 1ð 5 MOSS Off 9 2 ONLINE Figure 8 5 MOSS Changes of State MOSS Changes of State The following is a description of the events and actions that cause a MOSS state change Step numbers identify events and actions in Figure 8 5 Step 1 POWER ON RESET acco...

Page 358: ...rd check is presented to MOSS Step 8 A channel or program IPL request is presented to MOSS A CCU hard check is presented to MOSS Step 9 A MOSS abend occurred START panel request while the MOSS was in the OFFLINE ONLINE or ALONE state IML command entered at the console Step 10 If the reason to enter the MOSS DOWN state was an abend or an IML command entered at the console after MOSS re IML the fina...

Page 359: ...nd lower branch trace limits and with the branch trace table definition address in main storage and length The branch trace registers are located in CCU local storage The MOSS then requests the CCU to record the come from and go to information of any actual branch in the branch trace buffer The branch trace information is stored in two contiguous storage positions as follows Come From Bytes Go To ...

Page 360: ...nch trace buffer may contain extra records showing the entry and the exit of the CCU through some program level without instruction execution at that level Conditional Branch Trace The conditional branch trace allows to start and stop a branch trace from the control program itself without MOSS intervention The branch trace default values are initialized by MOSS at IPL time In order to avoid conten...

Page 361: ...X 3F8200 Line Adapter Mailboxes 512 bytes X 3F81FF X 3F8000 Top of Non Reserved Storage X 3F7FFF Exchange Time Outs The requestor fills in his mailbox and posts an interrupt to the receiver The receiver grants the interrupt decodes the mailbox contents posts a status in the mailbox and interrupts the requestor Throughout this time the mailbox is busy with the requestor A timer is used to provide a...

Page 362: ...6 Read Response in Mailbox Figure 8 7 Out Mailbox Exchange Procedure MOSS to CCU Communication In Mailbox The in mailbox is used to pass MOSS requests to the NCP PEP and for the NCP PEP to post the status response CCU CONTROL PROGRAM CCU STORAGE MOSS MICROCODE 1 Fill in Mailbox In Mailbox 2 Interrupt CCU on Level 4 3 Read Mailbox 4 Answer in Mailbox 5 In Mailbox 5 Interrupt MOSS on Level 4 5 6 Rea...

Page 363: ...Sollicited response Unsollicited reply Dump storage response Wrap test request Stop wrap test Connect line adapter Reissue a 3746 900 port swap Request buffer Free buffer MOSS offline MOSS online Port swapped Reconfiguration 84 Update CDS 01 Delete ports 02 Add ports 03 Delete line 04 Add line 05 Change CDS header 06 Insert CA 07 Delete CA 08 Change CA CA Services 93 94 95 96 Disconnect CA Connect...

Page 364: ...re listed in Table 8 4 NCP PEP BER transfer Buffers now available Wrap test results Time date valid Request a 3746 900 port swap Request Unit List Request unit RU sent by SSCP and processed by the MOSS Note Answered by a positive response or a sense code when negative response Refer to the Sense Code Appendix in the AOG Table 8 4 Request Unit List Hex Meaning 010331 Display storage answered by 010...

Page 365: ...h having an average of 100 SRL statuses The SRL out lines present their status to the following combinational logic at clock pulse B The resulting combinational logic values set the SRL In lines at the next clock pulse C LSSD Testing Circuit For testing purposes the above SRL Out are connected to SRL In lines in a sequential string as follows Figure 8 10 on page 8 18 The In and Out lines go to the...

Page 366: ... In Out 5 5 5 5 SRL 2 SRL 7 C B C B Clock Clock Figure 8 9 Simplified Data Flow In Out In Out In Out In Out 5 5 5 5 5 5 5 5 Scan In Scan Out 5 SRL ð 5 SRL 1 5 SRL 6 5 SRL 7 5 In A B A B A B A B Clock Clock Clock Clock Read SRLs Scan Register 5 5 ð 1 2 3 4 5 6 7 Set Reset SRLs Step Register Counts up to 256 Figure 8 10 LSSD Testing Circuit 8 18 IBM 3745 Models 130 150 160 170 and 17A Hardware Maint...

Page 367: ...EX and TRACK0 which are commun to both the HHD and the FDD READY line is doted on the MOSS board INDEX and TRACK0 are doted on the DFA card MOSS Board DFA Card FDD INDEX TRACKð READY HDD 2 Set or sense the file adapter registers 3 Seek head carriage 4 Engage the heads position the heads close to the disk diskette surface 5 Read data from the disk diskette 6 Write data to the disk diskette 7 Read b...

Page 368: ...ns on 3745 Model 17A refer to 3746 Model 900 Installation Guide and Service Processor Installation and Maintenance manuals Remote Support Facilities RSF The MOSS to RETAIN connection is made with a BSC protocol at 1200 2400 bps V 22 Bis or V 23 CCITT interface depending on the country via a duplex external modem with the auto answer feature The IBM RSF Modem operating characteristics are as follow...

Page 369: ...Control Panel Operation 9 5 Operator Consoles for Models 1x0 9 6 Highlights 9 6 Console Connection 9 8 3161 Console 3727 Console Key Conversion 9 8 Console Setup and Maintenance 9 8 Operator Consoles and Service Processor for Model 17A 9 8 Disk Diskette Drive 9 9 Hard Disk Drive HDD 9 9 Flexible Disk Drive FDD 9 10 Copyright IBM Corp 1989 1994 9 1 ...

Page 370: ...rries keys and indicators required for Controlling the power system Activating MOSS functions control panel test power bus test Hexadecimal display code to operator The 3745 control panel stays powered ON when the 3745 is powered OFF This allows information on power control and service to be displayed The Function Service and Power control keys allow the operator to scroll the different options Th...

Page 371: ...Control Panel Layout For code definitions refer to Appendix A in the MIP Figure 9 1 Control Panel Chapter 9 Control Panel Operator Consoles Disk Diskette Drives 9 3 ...

Page 372: ...Control Panel Reference Card Figure 9 2 Control Panel Reference Card 9 4 IBM 3745 Models 130 150 160 170 and 17A Hardware Maintenance Reference ...

Page 373: ... MOSS board and control panel see YZ pages Data Bus eight lines 5 Read Write 5 Keyboard Present Control Panel Select PCC 5 Reset Card 5 ð volt 5 28 volts EPO Power ON lamp 5 5 volts 5 PS2 28 volts 5 Control Panel Operation For control panel operation and tests refer to Basic Operations Guide and MIP Chapter 9 Control Panel Operator Consoles Disk Diskette Drives 9 5 ...

Page 374: ...eyboard overlay provided in shipping group IBM PS 2 able to run under OS 2 extended edition with Communication Manager emulating the 3101 Any equipment providing equivalent functions operating in IBM 3101 emulation mode For details about the consoles to be used on the 3745 refer to the Console Setup Guide SA33 0158 Remote Console Operates in duplex start stop mode at 1200 bps IBM 315x in the USA a...

Page 375: ...age 8 20 Consoles Tail Gate on Models 1X0 ð1R RSF Local Remote J1 J2 J3 The J1 connector is for the RSF console The J2 connector is for the remote or alternate console The J3 connector is for the local console See YZ pages for details For 3745 Model 17A ð1R A1 J1 The J1 connector is for service processor connection through the LAN Customer Power Control ð1H A3 J2 O J3 The J2 connector is for the c...

Page 376: ...ntain the 3745 17A and 3746 900 a new operator console is required The 3745 3746 900 operator console is a PS 2 based console fully con figured and loaded with microcode called MOSS extended MOSS E The oper ator console serves as service processor to the 3746 900 and the 3745 and must always powered On The console can operate up to four 3745 Models 17A to 61A but with a maximum of two of them equi...

Page 377: ...he heads are automatically parked in the landing zone when the power is OFF The hard disk drive is an FRU MOSS Board DFA Card To FDD See Note HDD J1 J2 DC Voltages From PS1 J3 J3 ñ i ñ Jumper for drive select set on position 1 Note Three Dot ORed lines INDEX READY and TRACK 0 are common to the HDD and the FDD Figure 9 4 HDD Connection For component locations see YZ pages For connector pin assignme...

Page 378: ...FF by the MOSS The diskette drive is an FRU with its own power supply MOSS Board FDD DFA J1 Card DC Voltages From PS1 J3 J2 ñ i To HDD See Note ñ Jumper for drive select set on position ð Note Three Dot ORed lines INDEX READY and TRACK 0 are common to the HDD and the FDD Figure 9 5 FDD Connection For component locations see YZ pages For connector pin assignment see page YZ542 Removal and Replaceme...

Page 379: ...Control 10 14 Power Control Subsystem 10 15 Power Control Data Flow 10 16 Power Control 10 17 Power Mode of Operation 10 20 Local Mode 10 20 Host Mode 10 20 Network Mode 10 20 Switching From One Mode to Another 10 21 Power ON OFF Sequence 10 22 Power ON Sequence 10 22 Power OFF Sequence 10 23 Scheduled Power ON Function 10 23 AC Detection and AC Monitoring 10 26 Air Flow Detector 10 27 Power ON Re...

Page 380: ...Power System in 3745 Models 130 150 160 and 170 Data Flow 10 2 IBM 3745 Models 130 150 160 170 and 17A Hardware Maintenance Reference ...

Page 381: ...Data Flow Figure 10 1 The Power System in 3745 Model 17A Data Flow For model 17A DMA and IOC buses are connected to the CBC in the 3746 900 This MLA card links the MOSS to the Service Processor through a LAN Chapter 10 Power System 10 3 ...

Page 382: ... supply 1 PS1 for DC voltages One power supply 2 PS2 for DC voltages to fans control panel and PCC card PS2 is located inside the primary power box Primary PS1 5 DC Voltages Power Box F H PS2 PCC MOSS H A Control Panel C Fan 1 K Fan 2 E x Component location on pages YZ010 and YZ011 10 4 IBM 3745 Models 130 150 160 170 and 17A Hardware Maintenance Reference ...

Page 383: ...40 volts See Figure 10 2 on page 10 6 for SW1 switch location Frequency The 3745 can operate at one of the following frequencies 50 Hz 1 Hz 60 Hz 1 Hz Safety Statement Input output cables must comply with the following safety statement For AC Voltage Input Hazardous voltage circuits with AC voltages input comply with IEC 950 Class I reinforced insulation For DC Voltage Outputs LIC type 5 or 6 are ...

Page 384: ...o PS1 J6 DC to fan 2 J7 DC to fan 1 J8 To UEPO switch J9 PS control to MOSS SW1 Voltage adjustment switch 2ðð 22ð or 24ð volts Figure 10 2 Primary Power Box Component Location Customer Plug The J2 connector is for the customer and provides a normal open contact when the power is OFF and reverse its state when the power is ON Electrical Characteristic 30 volts AC or 42 4 volts peak or DC at 20 to 5...

Page 385: ...EPO J6 28 V i Switch EPO2 i O i PCC 5 28 volts J7 F1 J9 MOSS Bd EPO3 i 5 V i PCC J8 J8 EPO4 i i J6 DC To Fan1 CP3 38 V i J7 DC To Fan2 Lines show hazardous areas where hazardous AC voltages are still present when power is switched OFF at the control panel See YZ pages for details Chapter 10 Power System 10 7 ...

Page 386: ...ð1F ð1A AC Volt J3 FDD HDD ð1B ð1D J4 Basic board ð1G J5 LIC board ð1M A2 J6 LIC board ð1M A1 J7 LIC board ð1L A1 J8 LIC board ð1L A2 TB1 TB3 See ñ Basic board TB2 TB4 See ò ð1G TB5 See ñ LIC boards TB6 See ò ð1L A1 and ð1L A2 ñ 5 volts level 6 ò 5 volts return level 6 See YZ pages for details 10 8 IBM 3745 Models 130 150 160 170 and 17A Hardware Maintenance Reference ...

Page 387: ... J1 see PS1 DC Voltage Test Points for pin assignment PS1 DC Voltage Test Points o 1 12 ð volts level 1 o 2 12 ð volts level 2 o 3 8 5 volts level 3 o 4 5 6 volts level 4 o 5 5 ð volts level 5 J1 o 6 5 ð volts level 6 o 7 5 ð volts level 7 o 8 5 ð volts level 8 o 9 8 5 volts level 9 o 1ð PS fault test o 11 OC fault test o 12 DC common Chapter 10 Power System 10 9 ...

Page 388: ...shall be used Using a scope with a larger bandwidth may give larger ripple values MOSS Board DC Voltages and Tolerances For test point pin locations see page YZ331 or YZ031 for ripple measurement Table 10 1 PS1 Voltages and Tolerances VDC Level Vmin Vmax J1 Test Pointñ 12 00 1 11 00 13 00 1 12 00 2 11 60 12 60 2 8 50 3 7 90 9 35 3 5 60 4 5 43 5 88 4 5 00 5 4 85 5 25 5 5 00 6 4 85 5 25 6 5 00 7 4 8...

Page 389: ...dapter number 3 DCREG located in 01G A1 ZE supplies HSS line adapter number 4 Basic Board PS1 DCREG 51 7 V HSS 3 5 V level 6 i i DCREG 51 7 V HSS 4 For DCREG card location see page YZ033 Table 10 3 Basic Board Voltages and Tolerances VDC Level Vmin Vmax Ripple 8 50 3 7 65 9 35 0 15 p p 5 60 4 5 43 5 88 0 10 p p 5 00 6 4 75 5 25 0 10 p p 5 00 8 4 70 5 50 0 10 p p 8 50 9 7 65 9 35 0 15 p p 1 70 ñ 1 ...

Page 390: ...C Voltages and Tolerances For test point pin locations see page YZ738 for LIB1 3 boards LICs 1 4 and page YZ739 for LIB2 board LICs 5 6 Table 10 4 LIC Boards 01M A1 and 01M A2 DC Volt ages and Tolerances VDC Level Vmin Vmax Ripple 8 50 3 7 65 9 35 0 15 p p 5 00 5 4 75 5 25 0 10 p p 5 00 8 4 70 5 50 0 10 p p 8 50 9 7 65 9 35 0 15 p p Table 10 5 LIC Boards 01L A1 and 01L A2 DC Voltages and Tolerance...

Page 391: ...witch J5 J8 i EPO Plugs F1 Fuse For details see YZ pages PS2 DC Voltages and Tolerances ñ These values are referenced to test point 01A A1 J3 pin 8 See page YZ331 for pin location ò This value is referenced to 01H B1 J6 J7 pin 1 See page YZ060 for connector location Table 10 6 PS2 Voltages and Tolerances VDC Vmin Vmax Test Point 5 00 4 75 5 25 01A A1 J3 pin 22ñ 28 00 24 90 29 50 01A A1 J3 pin 21ñ ...

Page 392: ... Disk and diskette can be also controlled manually DIF function 7 HDD ON OFF command FDD ON OFF command To ð1H J1 5V and 12V DC PS1 J3i iJ2 Diskette F B iJ3 Disk D HDD ON OFF command 5 4ð ms max Disk 5 V Level 7 12 V Level 1 FDD ON OFF command 5 4ð ms max Diskette 5 V Level 7 12 V Level 2 Disk Voltages and Tolerances From PS1 For DC test points see pages YZ Table 10 7 Disk Voltages and Tolerances ...

Page 393: ...r ON of the whole machine only in network mode The communication between the control panel and the MOSS The display on the control panel of the stacked power or fan faults The main line survey in order to detect AC main utility failures The automatic restart function on an AC main utility failure The diagnostic tests of the power control subsystem and the control panel The monitoring of the remote...

Page 394: ...D Driver Out LIC 5 Seq Complete 1 Bd 4 Power Pick 5 AC Fail FDD Power Hold ON OFF AC Sensing UEPO Sensing HDD Airflow Monitoring 3 ON OFF Battery Control Panel Bus 18 OC PS Fault Fault PS1 Control Panel Number of lines ñ One POR line per adapter ò Bypass MOSS diagnostic Figure 10 3 Power Control Data Flow 10 16 IBM 3745 Models 130 150 160 170 and 17A Hardware Maintenance Reference ...

Page 395: ...pplies PS1 and to the following signals Power pick and hold signals Sequence complete signal AC fault signal Air flow detectors outputs Remote power OFF signal Main contactor command UEPO sense Battery monitoring AC fail PCC Interconnection RPO PCC 5 5 MMIO Bus Power Pick 5 5 Power Hold 5 5 Control UEPO Panel Bus 5 5 MOSS Inop LED Driver Out 5 OC Fault PS1 Main Contactor Command 5 5 PS Fault PS1 S...

Page 396: ...5 Address Bit 9 Strobe Data from MOSS to PCC Card Data Read Write Address ð9 Strobe Less than 12 7 µs 5 XFERACK Data from PCC Card to MOSS Data Read Write Interrupt Level 2 Strobe Address ð9 Less than 12 7 µs 5 XFERACK 10 18 IBM 3745 Models 130 150 160 170 and 17A Hardware Maintenance Reference ...

Page 397: ...d Read Write 5 Keyboard Reset 5 LED Driver Out AC ON 5 PCC Card Control Panel Data Timing Select Read Write Data IN OUT 5 5 5 5 2ð ns 12ð ns 12ð ns 12ð ns Minimum Minimum Maximum PCC Card Power Supply Signal Interconnection Overcurrent Fault PCC PS1 Card Power Supply Fault HDD ON OFF 5 FDD ON OFF 5 Chapter 10 Power System 10 19 ...

Page 398: ...ed This plug prevents powering OFF the 3745 if the power control is set to position 1 host mode when no EPO cables are installed In this mode the automatic restart and power ON retry functions are available Network Mode In network mode 2 at the power control window and only in this mode the scheduled power ON function is available As for all the other communication controllers in this mode you can...

Page 399: ...etwork waiting for a manual power ON at the control panel or for a scheduled power ON action If an AC main utility fault occurs after switching from local to network the machine being OFF the automatic restart function will not apply If ON in local the machine will be maintained ON in network Switching from host to network The machine power ON OFF status is not impacted Switching from network to h...

Page 400: ... power supplies If no fault the reset lines are deactivated 100 ms later Then the disk HDD and the diskette FDD are powered ON MOSS IML will start and at the end of IML the MOSS will ask the PCC card which type of power ON was done local host network scheduled automatic restart the power ON time and the last power OFF time At the end of the power ON sequence and if the machine is in host mode the ...

Page 401: ...ion The purpose of the clock used in the power control subsystem is to keep time and calendar date through extended power OFF periods This will allow scheduled power ON actions to be taken at a predetermined time and day of the week independently of any intervening AC main power failures Each day of the week may be associated with a different power ON time The logic for the scheduled power ON func...

Page 402: ... function 0 service 0 Power ON Retry Function This function allows an automatic repower of the machine after an automatic power OFF due to any power supply or fan fault This function is only available in host and network modes The machine starts auto matically with a general IPL function 0 service 0 Retry Sequence 1 A fault is detected 2 The machine is powered OFF 3 The fault is displayed on the c...

Page 403: ...MOSS via the power control to perform selective resets for diagnostic purposes or a general reset at power ON The PCC card has 18 reset lines to reset the different machine adapters See Figure 10 3 on page 10 16 for details Chapter 10 Power System 10 25 ...

Page 404: ...ve 40 ms minimum with a duration lower than T2 45 ms b AC failure An AC failure longer than T2 45 ms The whole machine is powered OFF 2 Invalid AC failure The PCC card detects an AC failure but the AC is still present after two seconds false AC failure detection AC FAIL PS DC OUTPUT Tð T1 T2 T0 At this time the AC is going under the threshold T1 At this time the AC failure detection occurs T2 At t...

Page 405: ... to determine an eventual fault If a fault occurs during this scanning the machine is powered OFF this fault is displayed on the control panel and stacked in the PCC card After a 10 seconds wait the machine is powered ON again The same operation can be done three times After three times the machine stays power OFF Opto Coupler Device Output AFD 1 and AFD 2 5V 11 ms 5 AFD 0 5V 22 ms 5 Chapter 10 Po...

Page 406: ...el machine OFF due to three unsuccessful power ON This function allows to display the last four stacked faults This can be done only by entering service 1 prior entering the function B Faults Logging After any fault the power control sends a fault event to the MOSS If the MOSS is not operative this fault is stored in the PCC card and restored to the MOSS when it becomes operative 10 28 IBM 3745 Mo...

Page 407: ...el when active Voltage level is provided by the user Power ON Reset Paths MOSS Board PCC A15 A31 DFA ð1A Xð B2 ð1A Xð G2 A32 MPC A13 ð1A Xð E2 A31 MCC 1 A37 ð1A Xð H2 A31 MAC 2 A37 ð1A Xð H2 A31 MLA 2 ð1A Xð D2 1 For 3745 Models 1x0 2 For 3745 Model 17A Chapter 10 Power System 10 29 ...

Page 408: ...Yð A2Dð2 YR D13 Sð9 PCC PUC Xð B2 A16 Yð A2Bð2 YR B13 S13 V2 MO7 SCTL W2 Basic Board TRM MOSS board Basic Board ð1A ð1G A1 PCC B2ð Yð B2Bð6 YP Bð9 Pð4 TRM 1 Xð B2 L2 Pð4 TRM 2 P2 10 30 IBM 3745 Models 130 150 160 170 and 17A Hardware Maintenance Reference ...

Page 409: ...asic Board ð1A ð1G A1 A17 Yð A3Dð6 YPDð9 Dð2 PCC B15 Yð A3Bð8 YPBð7 CADR Xð B2 B16 Yð A3BO7 YPDð8 H2 C14 Yð A3Dð9 YPDð6 Dð2 CAL G2 Dð2 CADR F2 Dð2 CAL E2 Dð2 CADR D2 Dð2 CAL C2 Dð2 CADR B2 Dð2 CAL A2 Chapter 10 Power System 10 31 ...

Page 410: ...C C16 Yð A3Dð2 YPD13 CSC CSP Xð B2 C17 Yð A3Bð4 YPB11 T2 C18 Yð A3Dð3 YPD12 C19 Yð A3Bð5 YPB1ð C2ð Yð A3Dð5 YPD1ð Bð2 FESH EAC U2 Pð4 CSC CSP R2 Bð2 FESH EAC S2 Pð4 CSC Q2 Pð4 CSC P2 Pð4 CSC N2 Pð4 CSC M2 10 32 IBM 3745 Models 130 150 160 170 and 17A Hardware Maintenance Reference ...

Page 411: ...SS Board LIC Board 3 ð1A ð1L A2 LIC 5 6 Bð8 LIC 5 6 Bð8 SMUX B2 lower ð1L B2 A3Bð7 B17 pin C23 PCC Xð B2 C24 ð1L B1 A3Bð7 B17 Yð C3Að5 SMUX lower B2 pin Bð8 LIC 5 6 Bð8 LIC 5 6 6 LIC board 4 Chapter 10 Power System 10 33 ...

Page 412: ...on 3745 3746 900 power connection power control to the 3746 900 and information on the 3746 900 power refer to the 3746 Model 900 Hardware Maintenance Reference online documentation 10 34 IBM 3745 Models 130 150 160 170 and 17A Hardware Maintenance Reference ...

Page 413: ... Interrupts 11 25 MOSS Error Logging 11 29 Hexadecimal Codes 11 29 Hexadecimal Codes Versus MOSS BER ID 00 11 29 MOSS BERs Used With the IPL Application 11 33 MOSS BER Type 01 Summary 11 33 MOSS BER Type 01 ID 00 Detailed BER Display 11 39 MOSS BER Type 01 ID 00 Field Description 11 39 BER TYPE 01 ID 00 Error Code Description 11 40 MOSS BER Type 01 ID 01 11 50 MOSS BER Type 01 ID 01 Field Descript...

Page 414: ...1 ID 44 11 101 MOSS BER Type 01 ID 50 11 102 MOSS BER Type 01 ID 80 11 102 MOSS BER Type 01 IDs 91 B3 C1 C2 11 102 MOSS BER Type 01 IDs A0 to A4 Field Description 11 108 BER Formats on Disk 11 112 MOSS BERs Type 01 Formats 11 112 Diagnostics BER Type 03 11 123 Diagnostics BER Type 03 Summary 11 123 Diagnostics BER Type 03 Detailed BER Display 11 123 Diagnostic BERs Type 03 Formats 11 124 Power BER...

Page 415: ...Display 11 192 NCP PEP BER Type 12 Field Description 11 192 NCP PEP BER Type 12 Formats 11 193 NCP CCU BER Type 13 11 194 CCU BER Type 13 Summary 11 194 CCU BER Type 13 Detailed BER Display 11 195 CCU BER Type 13 Field Description 11 196 CCU BER Type 13 Formats 11 197 NCP IOC BER Type 14 11 198 IOC BER Type 14 Summary 11 198 IOC BER Type 14 Detailed BER Display 11 199 IOC BER Type 14 Field Descrip...

Page 416: ...BERs The event logging procedure of the MOSS reports each error caused by either an intermittent failure or a 3745 down controller re IPL Any such event in a 3745 subsystem is reported first to the NCP PEP and then to the MOSS for logging In this case a BER is built in a place called check record pool CRP where MOSS has access to it In some cases a BER is built directly by the MOSS itself In any c...

Page 417: ... abends or loss of resources on intermittent failures When the count is maintained by the Control Program the threshold values are found in the CDS at initialization each NCP IPL For the whole machine exhausting a threshold does not change the BER Table 11 1 Threshold Table Function or Adapter Threshold PIO CA 8 PIO LA 8 AIO 1 2 ADP CA 2 ADP LA 2 Unresolved Level 1 2 Unresolved Level 2 2 Unresolve...

Page 418: ... Automaint builds a reference code for each BER see page 11 16 BER Formatting The MOSS identifies the BER with a number and formats the information together with date time flag and other control bytes in the MOSS storage buffer as follows Notes 1 The MOSS formats the labels for BER display and supplies both date and time given via time services 2 The NCP date and time of the BERs may differ from t...

Page 419: ...on to MOSS processor are common for all BERs under I Os and to the power sub NCP PEP control system When the CCU or NCP PEP are When MOSS or the MOSS CCU down MOSS takes the control interface are down NCP PEP and creates corresponding records the error as BERs and BERs keeps in its CRP BER type ð1 ID ð1 ERR ð5 ð7 BER type ð1 IDs 91 B3 C1 C2 are the only non MOSS POWER are the only MOSS area BERs a...

Page 420: ...ased except in exceptional cases since It is not possible to erase individual BERs in the file but only the entire BER file The service personnel may need old BERs for history purposes The BER file when full writes the most recent BERs on the disk space used by the oldest BERs wraparound file When the BER file is erased a BER is logged to that effect in the file For more details see Service Functi...

Page 421: ...U related events errors when NCP PEP has control excluding CCU hardcheck 14 IOC bus related errors when not possible to attribute them to a specific adapter 15 TRSS events errors related to token ring subsystem operations BER ID The second byte identifies the category of error or event BER Created by the NCP PEP bit 0 Probable cause of the error OFF The most probable cause is the control program O...

Page 422: ...DIAG PWR ESS 3746 CA TSS NCP CCU IOC TRSS BER 9ðð HPTSS bus ð1 ð3 ð4 ð8 ð9 1ð 11 12 13 14 15 TYPE 1B 95 97 A2 BER IDs ERROR STATUS LCS LCS LCS Selected from the X Cð X C6 X CE ELD detail screen FRU list MUX FES in priority order LIC Figure 11 5 Example of a BER Tree Structure Note The error status is a predetermined field characteristic of the error BERs have a different error status according to ...

Page 423: ...perator 19 MOSS IML successful 2ð ð1 IPL complete without error 21 ð1 IPL started 24 Concurrent maintenance started 25 Concurrent maintenance ended 26 Concurrent maintenance cancelled 27 Concurrent maintenance rejected due to traffic 38 Concurrent maintenance NCP request to cancel ð3 ð1 Diagnostic started ð2 Diagnostic completed successfully ð4 ðA Power control mode change ðD Set time of day 14 Ai...

Page 424: ...leted with error and dump ð6 ð5 ð5 27 27 Re IPL due to hardw check ð6 ð5 ð5 2ð 2ð completed with error no dump Re IPL due to softw error ð6 ð5 ð7 41 41 completed W O error with dump 42 42 depends on abend code 47 47 Re IPL due to force dump from ð6 ð5 ð7 48 48 VTAM Re IPL for CP abend ð6 ð8 ð7 4ð 4ð Re IPL due to softw error ð6 ð5 ð7 46 46 completed OK no dump IPL re IPL completed ð6 ð3 ð1 D1 D1 D...

Page 425: ...r BER MOSS BER Level 1 received Nbr 6 CCU hardchk or CP abend Alarm notifying the user of the problem Figure 11 8 Example of a BER Alarm Alert Sequence Note that BERs are displayed in inverted chronological sequence most recent first BER Display There are three kinds of BER display screens ELD summary ELD list ELD detail When troubleshooting you should normally display the ELD summary then the ELD...

Page 426: ...in the X 76 U field of the IOC BER Table 11 5 References for ELD Detail Screen Type Meaning Created by Page Number 01 MOSS related BERs MOSS 11 39 to 11 96 All IDs except 91 B3 C1 C2 NCP PEP 11 102 03 Diagnostic MOSS 11 123 04 Power control MOSS 11 125 08 ESS related BER NCP PEP 11 137 09 3746 900 related BER NCP PEP 11 145 10 CA related BER NCP PEP 11 169 11 TSS related BER NCP PEP 11 184 12 NCP ...

Page 427: ...handler 01 03 11 56 CCA error handler 01 04 11 60 MOSS scanner 01 05 11 63 and 11 64 Events when no IPL 01 06 11 66 IPL Tasks 01 06 11 67 MOSS TRSS 01 07 11 78 CADS dump function 01 08 11 80 Disk function 01 10 11 12 11 81 and 11 82 Keyboard function 01 13 11 82 MIOC function 01 14 11 82 Mailbox interface function 01 15 11 82 MOSS CP Interface 01 16 11 83 RSF function 01 17 11 84 IML complete with...

Page 428: ... from MOSS to NetView through NCP and VTAM Then it is not unusual to have some alarms with no alert In addition for some specific cases only a panel hexadecimal error code is available Customers have to use the PDG service personnel will refer to the MIP Using the ELD function CEs and customers can have access to the complete list of alarms BERs reference code in the BER file itself through the MO...

Page 429: ... IPL complete or scanner re IML complete When applicable a valid or meaningful reference code must be retrieved from pre vious BER s and related alarm s In the PDG and according to the alarm number possible causes and recommended actions are given as for alerts The customer can fix the problem by himself for example CP sysgen error modem power OFF or The customer calls the IBM hardware central ser...

Page 430: ...sector The automatic analysis 5 is performed at this step of the BER process 6 Alarm and alert creation 6 Display and send the alarm alert 6 Write on the disk Figure 11 9 Automatic BER Analysis Process Flow Note Some BERs will never have an alarm alert even if they get a reference code and only those reference codes in alarms alerts must be considered first General Process Flow The automatic BER a...

Page 431: ...another CE Refer to the Service Functions manual for description and updating of that field BER Reference Code In case of a non permanent failure different BERs can be logged in the BER file at different times for this intermittent failure The automatic process gives for each BER a reference code pointing either at an FRU list or a software microcode problem Then the network operator can call the ...

Page 432: ... than a reference code given by the automatic correlation pointing to the most probably failing FRU s 1 or 2 Manual correlation is done in a range of BER sequence numbers selected by the CE whereas automatic correlation is done on a predefined time range No alarm alert is generated in manual correlation No reference code is generated Thus by looking at all BERs with or without alarm occuring at bo...

Page 433: ... of the values of D1 D2 D3 the other fields may provide different kinds of information See Figure 11 14 on page 11 23 after the 2 examples below Reference code related to a hardware problem D1 D2 D3 D4 D5 D6 D7 D8 B 4 ð 8 h h h h FRU group identifier 6 BER ID X ðð to X FF 6 BER type X 1 to X F 6 6 Identifier Pointer to Refcode file Always B except for diagnostics R Figure 11 11 Example of a Power ...

Page 434: ...ference code related to a software microcode problem D1 D2 D3 D4 D5 D6 D7 D8 ð ð X X If MOSS BER xx MOSS chk or 6 X X X X Abend code BER ID X ðð to to X FF 6 BER type Value according to the table below 6 Identifier Always B except for diagnostics R 6 Correlation between D2 and BER types D2 value I L P Q R S T U V W BER type ð1 ð4 ð8 ð9 1ð 11 12 13 14 15 Figure 11 13 Example of a Software Microcode...

Page 435: ...FRU logical number logical number CORRELATION G Associated FRU logical number FRUs H Associated INDEX 1 INDEX 2 DIAGNOSTICS R FRUs 3 ID FRU GROUP number K ID MOSS Check X FðFðFð no error X FðFðF1 B Z Type ID Meaningless DUMMY Program in Seq error Number Figure 11 14 Reference Code Structure Note ADAPT Nb is actually CA absolute number displayable digit 0 to F The FRU list associated to a FRU group...

Page 436: ...bsystem and the control program has identified the scanner concerned A specific communication scanner reports an error to the control program BER type 14 An error is detected while the control program is involved in a transaction with an adapter and no adapter can be identified as the source of the error Note A single intermittent error can be reported as BER types 10 11 or 14 depending on the tim...

Page 437: ...h 1 3 bus in check interface A 1 6 CADR card check interface A The following bits are checked in X 0 If none is ON the control program builds a BER 10 B1 0 0 normal initial selection interrupt 0 1 interface disconnect 0 2 selective reset 0 3 channel bus out check 0 5 stacked initial status 0 6 ESC status byte cleared 0 7 system reset Unresolved Level 3 CA Data Status BER 10 ID B2 The following bit...

Page 438: ...anner TSS or ESS Level 2 Unresolved BER 08 ID A1 BER 11 ID A1 There are 3 types of unresolved undefined interrupts A level 2 interrupt that occurs on a non SYSGENed line A level 2 interrupt from a SYSGENed line with the SCF SES and LCS all zero A level 2 interrupt from a SYSGENed line but the received status does not match the expected one CCU Level 1 Unresolved Interrupts BER 13 ID 91 The followi...

Page 439: ...on request X F bit 0 3 CA level 3 data status request X 7F bit 0 6 user interrupt request X 7F bit 1 5 internal timer level 3 X 7F bit 1 6 PCI level 3 Remote NCP If X 77 bit 1 0 or bit 1 1 is set and none of the following bits is set the control program builds a BER 13 B1 X 7F bit 0 6 user interrupt request X 7F bit 1 5 internal timer level 3 X 7F bit 1 6 PCI level 3 A BER 10 B7 is built if X 77 b...

Page 440: ...d with the adapter problem X 7E bit 0 7 IOC level 1 summary is ON Unresolved AIO Level 1 BER 14 92 X 7E bit 0 7 IOC level 1 summary is ON X 76 bit 0 6 adapter initiated operation is ON X 75 is invalid This is true when Either X 76 bit 0 2 IOC invalid CSCW is ON Or X 76 bit 0 4 IOC timeout is ON and IOC status X 76 bits 0 0 to 0 3 2 No response to TA tag or cycle steal grant Or X 76 bit 0 5 IOC bus...

Page 441: ... MOSS IML attempts within a given period of time MOSS level 0 interrupt ID 00 D00 DFF IML stop on disk diskette error doesn t force re IML D00 MOSS dump complete MOSS level 0 interrupt ID 00 MOSS level 0 re entry re IML MOSS level 0 interrupt MOSS level 0 re entry while in re IML MOSS level 0 interrupt F00 Start of MOSS dump F01 MOSS dump complete F10 F61 IPL check ID 00 ERR 06 Code to suspected F...

Page 442: ...ert bits bits ððððð PCA1 ð2 ððð PIO ðððð Bus check ðððð1 PCA2 ð2 ðð1 Device ope ððð1 Time out ððð1ð PCA3 ð2 ð1ð CHIO ðð1ð Storage ECC ððð11 MCCU A ð2 ð11 MMIO ðð11 Exception ðð1ð1 Unused 1ðð Other ð1ðð CHIO check ðð11ð MCAD ð2 1ð1 Unresolved ð1ð1 Internal check ðð111 DFA ð2 11ð MOSS program ð11ð Adapter check ð1ððð TOD ð2 ð111 PIRV ð1ðð1 MPWL ð2 1ððð Adapter down ð1ð1ð UC bus ð2 1ðð1 Pgm error ð1ð...

Page 443: ...d of the invoked command and calls when an error is found a control code function which stacks a second BER according to the called function Disk function Type ð1 ID 1ð 11 12 MOSS console Type ð1 13 MIOC function Type ð1 14 Mailbox interface function Type ð1 15 MOSS CP interface Type ð1 16 RSF MOSS function Type ð1 17 Then this function queues the composite BER in the buffer pool The com posite BE...

Page 444: ...ve MOSS function requests an I O operation but a hardware error is reported to MOSS level 0 and to the adapter code Level 0 handles the process and uses its own composite BER buffer The machine check micro code queues the composite BER in a buffer In this case the composite BER contains two BERs 4 No active MOSS function requests an I O operation but a hardware error is reported to the adapter Thi...

Page 445: ... field description MOSS retry NO NO 01 02 See MOSS 01 ID 02 field description MOSS retry NO NO 01 02 IOC operation error during MIOH CCU to MOSS status A register X 11 bit 0 MOSS retry NO NO 01 02 IOC operation error limit threshold MOSS down NO 03 01 03 Adapter clock check MCC status register 2 bit 4 MOSS retry NO NO 01 03 Adapter clock check limit threshold MOSS down NO 03 01 04 CCU clock check ...

Page 446: ... X 11 bit 0 MOSS fnct message 61 61 05 F0 MOSS scanner interface error Soft re IML OK dump KO Error detected by MOSS levels 1 or 4 when communicating with a scanner MCC status register 1 bit 6 at level 4 CCU to MOSS status A register X 11 bit 0 and X 76 bits 0 6 or 0 7 at level 1 MOSS funct message 65 65 05 F0 MOSS scanner interface error Soft re IML KO dump OK Error detected by MOSS levels 1 or 4...

Page 447: ...parameters passed by control program Errors in CA monitoring task Error found on the diskette which is not detri mental for the IPL Console or console adapter error Corresponding BERs are in the BER File There is a message on the console IPL com pletion D1 D1 06 04 LAxx Lines xxxx yyyy IML failed 6A 6A 06 05 05 NCP re IPL end and no dump MOSS creates this entry to end the re IPL and gen erates the...

Page 448: ...crocode action is dependent upon the kind of NCP IPL or IML error found see hexadecimal display IPL check Fxx NO 44 06 06 01 IPL complete with errors no dump on disk The MOSS microcode action is dependent upon the kind of NCP IPL or IML error found see hexadecimal display IPL check Fxx NO 49 06 07 MOSS offline request by operator MOSS offline B7 B7 06 08 05 NCP re IPL for CCU hardcheck CCU to MOSS...

Page 449: ... 13 24 Concurrent maintenance started C0 C0 25 Concurrent maintenance ended C1 C1 26 Concurrent maintenance cancelled C2 C2 27 Concurrent maintenance rejected due to traffic C3 C3 2A ESCA RE IPL failed 14 14 2B See ORIGIN field page 11 93 2C DL2 call completion NO NO 2D CP dump transfer error Dump purged NO NO 2E 3746 900 general IML 6C NO 2E LAN selective IML 6C NO 2E ESCA selective IML 6E NO 30 ...

Page 450: ...d in the BER file itself by looking at other BERs built by the MOSS which triggerred the MOSS inop bit in MCC status register MOSS down 03 NO A0 MOSS MOSS E token ring adapter error NO NO A1 MOSS MOSS E link lost 11 11 A2 MOSS MOSS E link re opened 12 12 A3 MOSS transient error NO NO A4 See page 11 106 for details NO NO B3 CP MOSS connection OUT mailbox command Time out at level 3 in control progr...

Page 451: ...t the PCAs hex codes A01 A0F the DFA or TOD hex codes A8D AAA and Dxx and MOSS BER Type 01 ID 80 DFA hh hh hh TOD hh PCA1 hh hh hh hh hh PCA2 hh hh hh hh hh PCA3 hh hh hh hh hh 2 Errors about the MCCU A hex codes A10 to A83 MCCU A hhhh hhhh hhhh hhhh hhhh hhhh SWAD ðððð not used 3 Errors about the MCAD without any register displayed hex codes A84 to A8C and AAB to CFF MCAD hh hh hh hh hh hhhh hh h...

Page 452: ... registers Page 11 46 SWAD Not used MCAD MCAD status registers Page 11 47 DFA DFA status registers Page 11 49 TOD TOD status register Page 11 49 REGS MOSS processor registers Page 11 46 MLA MOSS LAN adapter only for MOSS check 9800 page 11 49 BER TYPE 01 ID 00 Error Code Description The encoding of the MOSS CHECK bytes is explained on page 11 30 Table 11 11 Page 1 of 4 MOSS BER Type 01 ID 00 Error...

Page 453: ...HIO adapter check step counter parity CHIO adapter check hw burst counter parity CHIO adapter check CCU busy time out CHIO adapter check MIOC time out CHIO adapter check MIOC parity check in CHIO adapter check MIOC parity check out CHIO adapter check adapter failure CHIO adapter check multiple bits in STAT register CHIO adapter check no CHIO in progress in ACB CHIO multiple bits in EIRV CHIO no CH...

Page 454: ...bus check adapter failure PIO bus check adapter not detected PIO time out invalid command PIO time out outbound address parity check PIO time out outbound cmd data parity check PIO time out adapter failure PIO time out multiple bits in STAT register TOD AA6 AA7 AA8 AA9 AAA 4580 4000 4001 4010 4011 Adapter down PIO bus check inbound parity PIO bus check adapter not detected PIO time out outbound ad...

Page 455: ... unexpected on level 6 PIRV program request Unresolved AD3 AD4 AD5 AD6 AD7 AD8 AD9 ADA ADB ADC ADD ADE ADF AE0 AE1 AE2 AE3 AE4 AE5 AE6 AE7 9530 9531 9532 9533 9534 9535 9536 9537 9538 9539 953A 953B 953C 9550 9551 9552 9553 9554 9520 9521 9522 Exception address I fetch Exception address MS data access Exception fixed point overflow Exception inv addr on non MS access Exception multiple bits in DIV...

Page 456: ...ess X 7FFFFF or wrapped to zero 1 Error occurred during an instruction fetch 1 Fixed point overflow 1 External error loaded in EIRV DIV EIRV Error interrupt request vector 1 I O control check 1 Time out check 1 Storage data ECC check 1 Exception addr op spec 1 Channel I O check 1 Internal control check 1 Instruction address modifier IA points to the beginning of the instruction 0 Unused must be ze...

Page 457: ...nnel control vector 0000 0 Unused must be zero x Channel pointer number 0 CPR within set 12 15 1 CPR within set 8 11 x Indirect operation 0 Mode determined by bit 1 1 1 Indirect mode x 0 Short address 1 Long address CHCV byte 2 x 0 Write 1 Read x 0 Indirect mode Must be 0 if bit 0 6 is 1 1 Direct mode x x x x x CHCV pointer number x 0 CHCV 0 6 used 1 CHCV 0 6 not used IA Interrupted address byte 1...

Page 458: ...unter parity 1 MIOC CCU counter parity 1 HW burst counter parity 1 CCU busy time out 1 MIOC time out 1 MIOC parity check in 1 MIOC parity check out byte 2 1 Invalid PIO Cmd 1 UC bus parity check x Unused 1 MIOC busy 1 CHIO halt 1 Equipment check 1 Enable interrupt level 0 1 Interrupt level 0 read only MCCU A MCCU A status register 1 byte 3 xxxx x Unused 1 Enable CCU HLIR xx Unused byte 4 xxxx x Un...

Page 459: ... byte 12 xxxx xxxx CHCV register MCAD byte 1 MCAD INTP1 register 1 Invalid PIO command 1 UC bus parity check xx x Unused 1 Equipment check 1 Enable interrupt level 1 1 Interrupt level 1 MCAD byte 2 MCAD EINTP1 register 1 Enable timer 1 Enable CADS 5 8 HLIR xx Unused 1 100 ms timer 1 CADS 5 8 HLIR xx Unused MCAD byte 3 MCAD INTP4 register 1 Enable fault flags 1 Enable CADS 5 8 LLIR xx Unused 1 Faul...

Page 460: ...uest 1 Output request 1 DCE interrupt 1 Timer interrupt 1 Exception 1 Equipment check 1 Enable 1 Interrupt request byte 2 PCA1 2 or 3 A status register 1 Overrun 1 Underrun 1 Receive clock running 1 SDLC invalid sequence 1 SDLC flag 1 Invalid character 1 Break byte detected 1 Adapter in sync byte 3 PCA A control register 1 Receive mode 1 Transmit mode 1 Inhibit zero insert x x Mode select xx Code ...

Page 461: ... 00 Unused must be zero DFA byte 3 DFA interrupt status register 1 Termination error 1 Invalid command 1 Command reject 1 Parity error 1 Drive select high bit 1 Drive select low bit 1 ERP invoked 1 Equipment check TOD TOD status register 0000 0 Unused must be zero 1 Equipment check 1 Enable 1 Interrupt request SNAP Snapshot dump abend byte 1 000x xxxx Length of snapshot bytes 2 27 xxxx xxxx Dump M...

Page 462: ...pe 01 ID 01 Field Description Table 11 13 MOSS BER Type 01 ID 01 Field Description Field Name Meaning Refer to WHO In binary first part of error explanation Page 11 51 WHAT In binary second part of error explanation Page 11 51 ABEND Level 1 abend codes 4E Permanent HLIR 4F Too many spurious errors FF No abend code CMSA CCU to MOSS status register A X 11 CHECK Error Page 11 51 STATUS Level 1 status...

Page 463: ...s the type of error Unused Under diags CCU hardcheck Program IPL request Host IPL request Multiple IPL request I O error alert CCU stop IOC operation error Address exception Operation check CADS MIOH error Timer interrupt Unresolved CCU power OFF ESCA IPL request Check 00 01 02 03 04 05 06 07 08 09 0A 0B 0C 0D 0E 0F 10 11 No error on level 1 MOSS OK Adapter OK No error during CHIO Unable to reset ...

Page 464: ...MOSS BER ID 01 Note For the list of suspected FRUs refer to the MIP 11 52 IBM 3745 Models 130 150 160 170 and 17A Hardware Maintenance Reference ...

Page 465: ...ST hhhhhhhh hhhhhhhh hhhhhhhh hhhhhhhh NCP MB RESPONSE hhhhhhhh hhhhhhhh hhhhhhhh hhhhhhhh F1 END F2 MENU2 F3 ALARM F4 SUMMARY F5 LIST F7 PREVIOUS F8 NEXT á ñ MOSS BER Type 01 ID 02 Field Description Table 11 15 MOSS BER Type 01 ID 02 Field Description Field Name Meaning Refer to CMD Logical command used in the error description line Page 11 54 MOSS CHECK Error code used in the error description l...

Page 466: ...d MOSS CHECK 01 02 04 08 10 20 21 22 40 41 42 80 86 87 88 Error codes LSSD string select error Invalid PCW request Invalid out mailbox request In mailbox time out response Unexpected in mailbox response from CP Unresolved interrupt C clock stop Invalid interrupt level 4 CCU busy bit ON Devices busy bit ON CCU power down Physical error reported CHIO assynchronous error CHIO synchronous error CHIO t...

Page 467: ...04 02 01 81 82 83 Adapter control block flags Adapter down Adapter checkpoint retry Adapter Xparent retry thresh Time out on adapter Mail box in request Timer set for mail box in Moss Off line Cmd in mail box Moss On line Cmd in mail box CHIO opereation in process Timer set for CHIO ope CHIO retry has been done Chapter 11 Error Logging 11 55 ...

Page 468: ... Field Description Table 11 17 MOSS BER Type 01 ID 03 Field Description Field Name Meaning Refer to CMD Logical command Page 11 57 MOSS CHECK MOSS CHECK error codes Page 11 57 DEV Device in error Page 11 57 REQ Function request code reserved Page 11 57 ARC Adapter return code Page 11 59 BSTAT Basic status register Page 11 61 F Flag indicator last BCLE executed internal to MOSS Page 11 57 CMD Last ...

Page 469: ...te down CMD 00 01 02 03 04 05 Logical command Open Write Read Close Load Direct execute DEV 01 02 03 04 05 06 07 Adapter failure for disk operations Adapter failure for diskette operations Disk drive Diskette drive Adapter or disk drive Adapter or diskette drive Diskette media floppy disk REQ 00 05 07 25 83 A3 AB EB Function request code Execute Read operational statistics No op Read SCA state Ope...

Page 470: ...ails Field Name Bit Pattern or Hex Value Meaning SSB byte 0 1 1 1 1 1 x x 1 Drive status Drive ready Seek end HDD only Write protected FDD only Write fault HDD only Disk change Unused Track 0 SSB byte 1 x 1 1 1 1 1 1 1 SSB error status byte 0 CRC ECC error x 0 Data x 1 ID CRC ECC error Address mark not found Bad track Wrong cylinder Control address mark Format error ID not found SSB byte 2 x 1 1 1...

Page 471: ...2 13 PARAMETER PROBLEMS FRB program check BCL program check Invalid PIO command 20 28 HARDWARE AND EQUIPMENT CHECKS Undetermined equipment check hardware error in adapter Seek check 30 32 34 37 38 39 3A 3B 3C 3E DATA TRANSMISSION PROBLEMS Termination error with no specific error Sect buffer parity error Cylinder overrun HALT during a CHIO operation I O bus parity error CCB with no active CSB Inval...

Page 472: ...efer to ASTAT Adapter error status register Page 11 60 BSTAT CCA card basic status register Page 11 61 CMD Logical command Page 11 61 CSTAT Console status Page 11 61 MOSS CHECK Error code Page 11 62 MSTAT Modem status register Page 11 62 MOSS BER Type 01 ID 04 Field Details Some of the following fields may not appear on the ELD detail display but they are part of the BER and they are listed as the...

Page 473: ...ata lost overrun BSTAT 01 02 04 08 10 20 40 80 CCA basic status register bit assignment Adapter interrupt pending Adapter enabled MCPC interrupt Exception interrupt Timer interrupt Modem interrupt CSR output request CSR input request CMD 08 10 20 40 80 81 Logical commands Lock keyboard Close adapter Read write adapter Write adapter Open CCA adapter Open console CSTAT Bits 0 0 0 1 0 2 0 3 0 4 0 5 0...

Page 474: ...or local ASTAT adapter error Console error local Console error remote CAC detected exception ASTAT adapter exception status remote CAC detected error remote ASTAT adapter error MSTAT 01 02 04 08 10 20 40 80 CCA modem status register bit assignment CTS transition RLSD transitions Reserved DSR transition Ring indicator Received line signal detector RLSD Clear to send CTS Data set ready DSR 11 62 IBM...

Page 475: ...F8 NEXT á ñ Table 11 22 MOSS BER Type 01 ID 05 MOSS CHECK Details MOSS Check Meaning 01 Scanner failure during IPL 02 Mailbox contains the error status 04 Unexpected interrupt received 05 Scanner is inoperative 09 Scanner checkout failure 0A Scanner mailbox error status 0B Scanner time out 18 Scanner IML complete F0 Scanner dump and IML F1 Scanner IML and dump full F2 Scanner IML and disk error on...

Page 476: ...or description line REFER CODE IN CHAR CCCCCCCC MOSS CHECK Fð ADDR hh DUMP hh hh A hhhh hhhh hhhh hhhhhhhh hhhh B C D E F hhhh hhhh hhhh hhhhhhhh hhhh G H I J K F1 END F2 MENU2 F3 ALARM F4 SUMMARY F5 LIST F7 PREVIOUS F8 NEXT á ñ The field indicated by the letter A contains The DUMP error code in the first byte The IML error code in the second byte as follows Table 11 23 MOSS BER Type 01 ID 05 MOSS...

Page 477: ... in TA for dump C Last out TA for dump D Last TD for dump E Last MB for dump This field contains the first four bytes F Last disk ECB for dump G Last in TA for re IML H Last out TA for re IML I Last TD for re IML J Last MB for re IML This field contains the first four bytes K Last disk ECB for re IML MOSS BER Type 01 ID 05 Field Description Notes 1 All values are in hexadecimal notation X 0 to X F...

Page 478: ...tion line REFER CODE IN CHAR CCCCCCCC MOSS CHECK hh F1 END F2 MENU2 F3 ALARM F4 SUMMARY F5 LIST F7 PREVIOUS F8 NEXT á ñ Note For software information on BERs originated by NCP PEP refer to the associated product documentation MOSS BER Type 01 ID 06 Error 03 or 06 This BER corresponds to one of the following cases IPL check IPL complete errors For IPL complete with errors the BER is always normal i...

Page 479: ...hhh hh hhhh hhhh hh hhhh hhhh hh hhhh hhhh hh hhhh hhhh hh hhhh hhhh hh hhhh hhhh hh hhhh hhhh hh hhhh hhhh hh hhhh hhhh hh hhhh hhhh hh hhhh hhhh hh hhhh hhhh hh hhhh hhhh hh hhhh hhhh hh hhhh hhhh hh hhhh hhhh hh 3746 9ðð hhhh F1 END F2 MENU2 F3 ALARM F4 SUMMARY F5 LIST F7 PREVIOUS F8 NEXT á ñ MOSS BER Type 01 ID 06 Error 04 BER format foM7a see page 11 114 The MOSS microcode generates the fol l...

Page 480: ...ul after CCU hard check or NCP abend Check CCU hard check NCP abend CLDP abend Timed IPL will occur soon Timed IPL is cancelled LSSD string first part LSSD string second part IPL info 01 IPL CCU 01 Always set to 01 REQ 01 02 03 04 05 06 07 08 09 0A 0B IPL on power On reset CCU scanners IPL req from KBD Unused Unused Unused Unused IPL is requested by the level 1 Scheduled or network power On reset ...

Page 481: ...Led no action stop go connect disconnect reset performed and no scanner error detected scanner is initialized Unused HPTSS ESS found present in the CDF LA byte 3 x1 x identifies the type of LA 1 TSS 2 HPTSS 3 TRSS 6 ESS The second digit is always set to 01 LA byte 4 01 02 03 04 05 06 07 08 09 0A 0B 0C 0D 0E 0F to 15 Mismatch between CDF and data returned from the scanner MUX presence and EXTEND bi...

Page 482: ...Bad branch trace buffer length Bad check record pool Bad control program interface table level 1 on CA during CA monitoring X71 register is not readable CLDP did a pseudo abend Loading scanner table failed phase 3 Control info length error MB error F2 byte 2 x x x x x x x x x x IPL from disk length error MB error IPL complete with port swap errors LSSD dump incorrect Adapter dump requested not per...

Page 483: ... is valid IN76 is valid IN7D is valid IN7E is valid IN7X is valid Bytes 4 6 IAR Bytes 7 9 SAR Bytes 10 12 LAR Bytes 13 14 INPUT X 70 Bytes 15 16 INPUT X 76 Byte 17 x x x x IN76 IOC1 STATE LATCH See page 2 35 Time out Bus IN parity AIO PIO Byte 18 Unused Bytes 19 20 INPUT X 7D Bytes 21 22 INPUT X 7E Bytes 23 24 INPUT X 7E extension F1 x x x x x x x x Disk IPL facility failed PCA of local console no...

Page 484: ...et to 01 Byte 6 Unused IPLCHECK Byte 1 Byte 2 0000 1111 x x x x x x x x Error 03 only IPL complete with errors Unexpected IPL option Unexpected CCU option Unexpected undefined F key No CCU under IPL IPL started No CCU specified for BER Unused Unexpected display request Unused 3746 900 8 h h h 4 h h h 2 h h h 1 h h h Bad NCP version for the 3746 900 Coupler ready bit No port swap exchange Port swap...

Page 485: ...ð6 3745 RE IPL STARTED FOR CCU HARDCHECK REFER CODE IN CHAR CCCCCCCC MOSS CHECK ð8 EVENT EXT ð5 CCU hh IAR hhhhhh LAR hhhhhh SAR hhhhhh X7ð hhhhhh X76 hhhhhh X7D hhhhhh X7E hhhhhh HDCK hhhh F1 END F2 MENU2 F3 ALARM F4 SUMMARY F5 LIST F7 PREVIOUS F8 NEXT á ñ MOSS BER Type 01 ID 06 Errors 05 08 Ext 05 07 Field Details Table 11 28 MOSS BER Type 01 ID 06 Errors 05 or 08 Field Details Field Name Bit Pa...

Page 486: ... 06 Error 09 BER format foM10 see page 11 114 The MOSS microcode generates the fol lowing BER when CLDP abends code X F1B This BER does not follow the composite BER mechanism The X72 field contains the CLDP abend code à ð ELD DETAIL SEL hhh FLAG hh DATE hh hh TIME hh hh TYPE ð1 ID ð6 APPL error description line REFER CODE IN CHAR CCCCCCCC MOSS CHECK ð9 EVENT EXT hh CCU hh IAR hhhhhh X71 hhhhhh X72...

Page 487: ... error status idem LA LA error status idem MOSS BER Type 01 ID 06 Error 09 Field Details Some of the following fields may not appear on the ELD detail display but they are part of the BER and they are listed as they appear in the BER file See the section BER Formats on Disk page 11 112 Table 11 30 MOSS BER Type 01 ID 06 Err 09 Field Details Field Name Bit Pattern or Hex Value Meaning X71 bytes 0 1...

Page 488: ...PL is cancelled à ð ELD DETAIL SEL hhhh FLAG hh DATE dd dd TIME dd dd TYPE ð1 ID ð6 CP error description line REFER CODE IN CHAR CCCCCCCC MOSS CHECK 14 CCU hh LOAD MODULE xxxxxxxx TIMED IPL DATE TIME MM DD YY HH MM REFERENCE DATE TIME MM DD YY HH MM MOSS CANCEL ORIGIN hh F1 END F2 MENU2 F3 ALARM F4 SUMMARY F5 LIST F7 PREVIOUS F8 NEXT á ñ MOSS BER Type 01 ID 06 Error 18 Format foM47 see page 11 121...

Page 489: ...ER Type 01 ID 06 Errors 13 and 14 Field Description Table 11 31 MOSS BER Type 01 ID 06 Errors 13 and 14 Field Details Field Name Bit Pattern or Hex Value Meaning CCU hh 01 hh 02 CCU A CCU B LOAD MODULE xxxxxxxx Load module name eight characters max TIMED IPL DATE TIME MM DD YY HH MM Date and time of the timed IPL REFERENCE DATE TIME MM DD YY HH MM Host date and time reference when the timed IPL co...

Page 490: ...GISTER bbbbbbbb bbbbbbbb F1 END F2 MENU2 F3 ALARM F4 SUMMARY F5 LIST F7 PREVIOUS F8 NEXT á ñ Table 11 32 MOSS BER Type 01 ID 07 Field Details Field Name Bit Pattern or Hex Value Meaning ERROR hh 04 hh 08 hh 40 hh 80 Error description No interrupt from TRM Error detected on level 1 Error detected on level 4 Error detected on level 1 TRA ADDR hhhh TRA address see page 3 46 GET COMMAND COMPLETION hhh...

Page 491: ...occurs on the MOSS TRSS interface à ð ELD DETAIL SEL hhhh FLAG ðð DATE ð4 29 TIME 23 45 TYPE ð1 ID ð7 ERROR DESCRIPTION REFER CODE IN CHAR CCCCCCCC ERROR FF ERROR EXT hh TRA NBR hh TIC NBR hh CCU hh TRA ADDR hhhh F1 END F2 MENU2 F3 ALARM F4 SUMMARY F5 LIST F7 PREVIOUS F8 NEXT á ñ Table 11 33 MOSS BER Type 01 ID 07 Field Details Field Name Bit Pattern or Hex Value Meaning ERROR 00 FE Error descript...

Page 492: ... occurs on the MOSS CA interface à ð new BER not yet entered ELD DETAIL SEL hhhh FLAG ðð DATE dd dd TIME hh hh TYPE ð1 ID ð8 ERROR DESCRIPTION REFER CODE IN CHAR CCCCCCCC DUMP hh TRACE hh CA hh CCU hh F1 END F2 MENU2 F3 ALARM F4 SUMMARY F5 LIST F7 PREVIOUS F8 NEXT á ñ MOSS BER Type 01 ID 08 Field Details Table 11 35 MOSS BER Type 01 ID 08 Field Details Field Name Hex Value Meaning DUMP 00 01 02 03...

Page 493: ...ning ERR CODE FF Always set to FF ERROR EXT 00 01 02 03 Other Error extension description Dump successfully completed Dump file already full Dump failed disk error Dump failed adapter error Dump failed unknown cause ELA NBR hh ELA number 01 08 ELA ERR STATUS hh CCU 01 CCU always set to 01 MOSS BER Type 01 IDs 10 and 11 Format foM14 see page 11 116 à ð ELD DETAIL SEL hhhh DATE dd dd TIME dd dd TYPE...

Page 494: ...12 The IORB field pattern changes according to the BER ID ID 13 hhhh hhhh hhhhhhhh hh hh hh hh hhhhhhhh hhhhhhhh hhhhhhhh hhhh hhhh hh ID 14 hhhh hhhh hhhhhhhh hh hh hh hh hhhhhhhh MOSS BER Type 01 ID 15 Format foM30 see page 11 118 MOSS CP interface mailbox à ð ELD DETAIL SEL hhhh FLAG hh DATE dd dd TIME dd dd TYPE ð1 ID 15 CP error description line REFER CODE IN CHAR CCCCCCCC IORB hhhh hhhh hhhh...

Page 495: ...h DATE dd dd TIME dd dd TYPE ð1 ID 1E ERROR DESCRIPTION REFER CODE IN CHAR CCCCCCCC IORB hhhh hhhh hhhhhhhh hh hh hh hh hhhhhhhh hhhhhhhh OC1 CCCCCCCC OC2 CCCCCCCC CCUF CCCCCCCC CCUB CCCCCCCC F1 END F2 MENU2 F3 ALARM F4 SUMMARY F5 LIST F7 PREVIOUS F8 NEXT á ñ MOSS BER Type 01 IDs 10 to 16 and 1A to 1E Field Description For information on BERs originated by NCP PEP refer to the associated product d...

Page 496: ...STAT hh F1 END F2 MENU2 F3 ALARM F4 SUMMARY F5 LIST F7 PREVIOUS F8 NEXT á ñ MOSS BER Type 01 ID 17 Field Description Table 11 38 MOSS BER Type 01 ID 17 Field Description Field Meaning Refer to A STAT Adapter status register page 11 61 B STAT Adapter status register page 11 61 BCLE Buffer control list element Page 11 86 CMD Logical Cmd in the request function Page 11 86 C STAT Adapter status regist...

Page 497: ...tion transient area module name 8 bytes CCUB Unused CDF RC CDF return code Normally 0000 otherwise PE only For PE only CMD Logical Cmd in the request function Page 8 15 ECBDISK ECB on disk diskette operation PE only F Error code Information is collected in case hexadecimal code cannot be displayed on the panel Page 11 88 MIOC CCUA B MIOC ECB for operation on CCUA B Page 11 87 PANEL HEXCODE Hexa co...

Page 498: ...ld Details Some of the following fields may not appear on the ELD detail display but they are part of the BER and they are listed as they appear in the BER file See the section BER Formats on Disk page 11 112 Table 11 40 Page 1 of 4 MOSS BER Type 01 IDs 17 19 and 20 Field Details Field Name Bit Pattern or Hex Value Meaning BCLE 00 01 03 04 06 0C 10 14 16 1E 3C 80 Buffer control list element Enable...

Page 499: ... I O running Request truncated CCU busy bit On Failed IOC error NCP time out Mail box lock LSSD error residual count String select error No mail box allowed CCU IPL Buffer empty MIOC adapter busy bit On MOSS address exception MOSS OP check CHIO asynchronous error CHIO time out STAT Mail box status Byte 1 80 40 20 10 08 04 02 01 Accepted Rejected Not used Not used Keep buffer Free buffer Not used N...

Page 500: ...vice mode In such a case default values are Origin MOSS power ON Function MOSS IML from disk Service CE mode Unused F x x xx xxx x Error code IML not successful Alarm indicator A0 has to be generated Unused Operation with power failed for x Get end of IML data x Get stacked error record x Panel hex display Unused FUNCTION 00 01 02 05 07 08 09 0A Function selection General IPL with IML from disk MO...

Page 501: ...sed IPL is requested by the level 1 Scheduled or network power ON reset IPL after fallback Manual fallback requested IPL of the stanby CCU requested Timed IPL requested LVLE REQ 0000 0010 0000 0111 0000 0011 0000 0100 Identification of CCU IPL request CCU hardcheck Output 70 received Program request IPL Channel request IPL CONF 01 Always set to 01 DEFAULT 01 Always set to 01 MODE 01 Always set to ...

Page 502: ... á ñ MOSS BER Type 01 ID 21 Field Details Some of the following fields may not appear on the ELD detail display but they are part of the BER and they are listed as they appear in the BER file See the section BER Formats on Disk page 11 112 Table 11 41 MOSS BER Type 01 ID 21 Field Details Field Name Bit Pattern or Hex Value Meaning EVENT EXT 01 IPL STATUS xxxx xx x x Unused IPL mode IPLMODE x 0 Ope...

Page 503: ...page 11 120 à ð ELD DETAIL SEL hhh FLAG hh DATE dd dd TIME dd dd TYPE ð1 ID 2A ERROR DESCRIPTION REFER CODE IN CHAR CCCCCCCC TA hh SLID hhhhhhhh CCU hh F1 END F2 MENU2 F3 ALARM F4 SUMMARY F5 LIST F7 PREVIOUS F8 NEXT á ñ MOSS BER Type 01 ID 2B This BER is generated when a RE IPL has started on a line a CA or an ESCA Format foM39 see page 11 120 à ð ELD DETAIL SEL hhh FLAG hh DATE dd dd TIME dd dd T...

Page 504: ... hhh FLAG hh DATE dd dd TIME dd dd TYPE ð1 ID 2D ERROR DESCRIPTION REFER CODE IN CHAR CCCCCCCC CCU hh REASON hh F1 END F2 MENU2 F3 ALARM F4 SUMMARY F5 LIST F7 PREVIOUS F8 NEXT á ñ MOSS BER Type 01 ID 2E This BER is generated for a CP dump transfer error the dump is purged Format foM50 see page 11 122 à ð ELD DETAIL SEL hhh FLAG hh DATE dd dd TIME dd dd TYPE ð1 ID 2E ERROR DESCRIPTION REFER CODE IN...

Page 505: ...xxxx Alarm 16 SLID System logical ID TA Page 3 36 TD Page 3 36 COMPLETION CODE 01 02 03 04 05 Call RETAIN not successful Call RETAIN not authorized Call RETAIN OK hardware problem Call RETAIN OK microcode problem plus fix down loaded to MOSS E Call RETAIN OK microcode problem without fix CPN ccc Customer problem number REASON 01 02 03 04 05 LAN error link down MOSS E microcode error HDD disk error...

Page 506: ...DETAIL SEL hhhh FLAG hh DATE dd dd TIME dd dd TYPE ð1 ID 3ð APPL error description line REFER CODE IN CHAR CCCCCCCC FRU GROUP hhhh F1 END F2 MENU2 F3 ALARM F4 SUMMARY F5 LIST F7 PREVIOUS F8 NEXT á ñ MOSS BER Type 01 ID 32 Format foM27 see page 11 117 MCAD error à ð ELD DETAIL SEL ddd FLAG hh DATE dd dd TIME dd dd TYPE ð1 ID 32 APPL error description line REFER CODE IN CHAR CCCCCCCC PLIST hhhhhhhh ...

Page 507: ...ommand sent to adapter MOSS BER Type 01 ID 36 Cyclic hour notification à ð ELD DETAIL SEL ddd FLAG hh DATE dd dd TIME dd dd TYPE ð1 ID 36 APPL error description line REFER CODE IN CHAR CCCCCCCC F1 END F2 MENU2 F3 ALARM F4 SUMMARY F5 LIST F7 PREVIOUS F8 NEXT á ñ MOSS BER Type 01 ID 38 Format foM28 see page 11 118 CA concurrent maintenance NCP request to cancel à ð ELD DETAIL SEL ddd FLAG hh DATE dd...

Page 508: ...or code 2 contains CCU INPUT X57 return from MOSS Page 11 96 IOIRV I O interrupt request vector Page 11 44 PIRV Program interrupt request vector Page 11 44 PIC Controller IPL type REQ Mailbox information MOSS BER Type 01 IDs 38 and 39 Field Details Table 11 44 MOSS BER Type 01 ID 39 Field Details Field Name Bit Pattern or Hex Value Meaning CCU INPUT X57 Byte 0 x x x x xxxx CA 5 MOSS request pendin...

Page 509: ...MOSS BER Type 01 ID 43 Field Details The data are displayed in hexadecimal form The next table gives the bit correspondance of the fields referenced in the previous picture Table 11 45 Page 1 of 5 MOSS BER Type 01 ID 43 Field Details Field Name Bit Pattern Meaning A Panel and Miscellaneous Warnings Byte 1 x x x x x x x x Problem suspected with hexadecimal display ROS 8K entry wrongly selected Info...

Page 510: ...ted level 0 IR in PCA3 test PCA3 internal wrap asynchronous test KO Unexpected interrupt during PCA3 test Unused C to P MCAC test warnings C IPL and adapters information Byte 1 x x x x xx x x Unused MCAD KO Unused MCCU KO Unused IPL not possible on CCU Unused Byte 2 x x x x xxxx Unused MCAD usable Unused MCCU usable Unused D Byte 1 MCAD errors x x x x x x xx Valid PIO unrecognised by MCAD Valid PI...

Page 511: ...its ON in MCAD F Reset CADS information Byte 1 xxxx x x x x Unused M reset CADS 5 ON M reset CADS 6 ON M reset CADS 7 ON M reset CADS 8 ON Byte 2 Unused G Enable CADS possibilities Byte 1 xxxx x x x x Unused Enable CADS 5 not possible Enable CADS 6 not possible Enable CADS 7 not possible Enable CADS 8 not possible Byte 2 Unused H Reset CADS possibilities Byte 1 xxxx x x x x Unused Reset CADS 5 not...

Page 512: ...not OK Sense CADS 7 presence not OK Sense CADS 8 presence not OK L CADS interface state Byte 1 xxxx x x x x Unused Interface with CADS 5 KO Interface with CADS 6 KO Interface with CADS 7 KO Interface with CADS 8 KO Byte 2 Unused M Miscellaneous MCAD errors Byte 1 xx x x xxxx Unused M force error impossible in MCAD Unused Byte 2 Unused N MCCU errors Byte 1 x x x x x xxx Valid PIO unrecognised by MC...

Page 513: ...M card ID not available for MCC M IOC tag reset function unusable M disable IOC bus not usable M watchdog mechanism KO in MCCU Byte 2 Unused MOSS BER Type 01 ID 44 à ð ELD DETAIL SEL ddd FLAG hh DATE dd dd TIME dd dd TYPE ð1 ID 44 MOSS CODE DATA FOR PROBLEM ISOLATION CCCCCCCC hhhhhhhh hhhhhhhh hhhhhhhh hhhhhhhh hhhhhhhh hhhhhhhh hhhhhhhh hhhhhhhh hhhhhhhh hhhhhhhh hhhhhhhh hhhhhhhh hhhhhhhh hhhhhh...

Page 514: ... ID 00 11 39 MOSS BER Type 01 IDs 91 B3 C1 C2 Format foM8 see page 11 114 The NCP PEP program level 4 generates BERs 91 B3 C1 and C2 if a MOSS error occurs during a mailbox exchange This BER is transferred to MOSS if MOSS successfully recovers from the MOSS error These BERs should always be accompanied by MOSS BER IDs 00 01 02 or 03 When BER ID 91 is not accompanied by one of these BERs it only me...

Page 515: ...is BER is generated for a MOSS MOSS E link problem Format fom41 see page 11 120 à ð ELD DETAIL SEL hhh FLAG hh DATE dd dd TIME dd dd TYPE ð1 ID Að ERROR DESCRIPTION REFER CODE IN CHAR CCCCCCCC REASON hh PANEL CODE ccc F1 END F2 MENU2 F3 ALARM F4 SUMMARY F5 LIST F7 PREVIOUS F8 NEXT á ñ MOSS BER Type 01 ID A2 This BER is generated for a MOSS MOSS E link re opened problem Format fom42 see page 11 120...

Page 516: ... ð ELD DETAIL SEL hhh FLAG hh DATE dd dd TIME dd dd TYPE ð1 ID A3 ERROR DESCRIPTION REFER CODE IN CHAR CCCCCCCC MOSSCHK ð2 SLID hhhhhhhh YYSTATUS hh TYPE hh IA hhhhhhhh RCV MSG hhhhhhhh hhhhhhhh hhhhhhhh hhhhhhhh hhhhhhhh hhhhhhhh hhhhhhhh hhhhhhhh hhhhhhhh hhhhhhhh hhhhhhhh hhhhhhhh hhhhhhhh hhhhhhhh hhhhhhhh hhhhhhhh hhhhhhhh hhhhhh F1 END F2 MENU2 F3 ALARM F4 SUMMARY F5 LIST F7 PREVIOUS F8 NEXT...

Page 517: ...E dd dd TIME dd dd TYPE ð1 ID A3 ERROR DESCRIPTION REFER CODE IN CHAR CCCCCCCC MOSSCHK ð5 SLID hhhhhhhh TRANID hhhhhhhh REQUEST hh hhhhhhhh hhhhhhhh RESPONSE hhhhhhhh IA hhhhhhhh F1 END F2 MENU2 F3 ALARM F4 SUMMARY F5 LIST F7 PREVIOUS F8 NEXT á ñ This BER is generated for an expected message not received à ð ELD DETAIL SEL hhh FLAG hh DATE dd dd TIME dd dd TYPE ð1 ID A3 ERROR DESCRIPTION REFER COD...

Page 518: ...nerated when DLC or MAC counters are different of zero and when one of the MAC counters is 80 or when XMIT ERR or RCVD ERR counter is 80 à ð ELD DETAIL SEL hhh FLAG hh DATE dd dd TIME dd dd TYPE ð1 ID A4 ERROR DESCRIPTION REFER CODE IN CHAR CCCCCCCC DLC COUNTERS XMIT COUNT hhhh RCVD COUNT hhhh XMIT ERR hh RCVD ERR hh T1 EXPIRED hhhh RCVD CMD hh SEND CMD hh PRMY STATE hh SCDY STATE hh STATION VS hh...

Page 519: ...hh STATION VR hh STATION VA hh PAGE 2 OF 2 F1 END F2 MENU2 F3 ALARM F4 SUMMARY F5 LIST F7 PREVIOUS F8 NEXT á ñ This second page is generated when the DLC counters are to zero and when one MAC counter is different of zero à ð ELD DETAIL SEL hhh FLAG hh DATE dd dd TIME dd dd TYPE ð1 ID A4 ERROR DESCRIPTION REFER CODE IN CHAR CCCCCCCC MAC ERR COUNTERS LINE hh INTERNAL hh BURST hh ARI FCI hh ABORT DEL...

Page 520: ...n phase See page 11 110 TYPE FRB type in error See page 11 111 CAUSE MOSS check cause See page 11 111 REQUEST Previous request summary RESPONSE SSA command header SERVER NAME Server name IA Instruction address MAJRQCOD Major request code MINRQCOD Minor request code MAJRCCOD Major return code MINRCCOD Minor return code OPENERRC Open error code RINGSTAT Ring status LINKSTAT Link status LAN STATUS LA...

Page 521: ... control blocks initialization by the IML processor Forced selection This bit is set ON when the MOSS diags cannot get from the MPWL valid information defining the origin the function or service mode In such a case default values are Origin MOSS power ON Function MOSS IML from disk Service CE mode Unused FUNCTION 00 01 02 05 07 08 09 0A Function selection General IPL with IML from disk MOSS IML fr...

Page 522: ...knowledged FRMR received SABME received TI timer expired FRMR sent Unexpected SABME received Permanent ring beaconing Lobe wire fault Auto removal while beacon Remove received Auto removal FSM time out MOSSCHK BER 01 ID A3 01 02 03 04 05 06 Invalid PICA message FSM error Invalid routing Invalid server name Unmatched SSA response Expected message not received MOSSCHK BER 01 ID A4 01 02 03 04 MOSS M...

Page 523: ...o A4 Field Details Field Name Hex Value Meaning TYPE 01 02 03 04 PICA SSA Server connect Server disconnect CAUSE 01 02 03 04 05 06 Not supported ILTOP Not supported POC Invalid path value Not supported PICA message SSA time out FSM time out Chapter 11 Error Logging 11 111 ...

Page 524: ...sed 45 Unused 6ð 61 CCUA CP abend 46 49 IA 62 63 CCUA TA 5ð 53 PSCI 64 85 Unused 54 57 OP 86 STATUS 58 1ð5 Regs interrupt LVL 87 Unused 1ð6 1ð7 CHCV 88 89 CCUA CP abend 1ð8 1ð9 Register space 9ð 91 CCUA TA 11ð 113 Main storage loc 92 1ð3 MCAD REGS 114 117 CHIO current 1ð4 Map of register 118 119 DUMP value 12ð MOSS dump stat 1ð5 CCU for CADS 121 EIRV 1 1ð6 IOC for CADS 122 IORV 1 1ð7 NUM for CADS ...

Page 525: ...49 Unused 58 69 SSB 5ð 53 ADDR 7ð 77 FILE mod name 54 65 PCW 66 Flags ACB Format foM2b ID ð2 Byte Meaning 1 27 Header 28 29 TYPE ID 3ð MOSS CHECK 31 CMD 32 47 NCP MB REQUEST 48 63 NCP MB RESPONSE Format foM4 Format foM5 ID ð4 ID ð5 MOSS Check ðð ð1 ð2 ð4 ð5 ð8 1ð 2ð 4ð 8ð FF Byte Meaning Byte Meaning 1 27 Header 1 27 Header 28 29 TYPE ID 28 29 TYPE ID 3ð MOSS CHECK 3ð MOSS CHECK 31 CMD 31 ADDR 32 ...

Page 526: ... 182 F2 183 185 X71 186 188 X72 189 IPL mode ID ð6 19ð 192 CCU configuration 193 216 MIS Error ð6 MOSS Check ð1 ð2 217 F1 218 219 RC from CDF Byte Meaning 22ð 315 CA 316 317 IPLCHECK 1 27 Header 318 Unused 28 29 TYPE ID 319 3746 9ðð 3ð MOSS CHECK Format foM7a Format foM8 ID ð6 IDs 91 B3 C1 C2 MOSS Check ð4 Byte Meaning Byte Meaning 1 27 Header 1 27 Header 28 29 TYPE ID 28 29 TYPE ID 3ð MOSS CHECK ...

Page 527: ...ing Byte Meaning 1 27 Header 1 27 Header 28 29 TYPE ID 28 29 TYPE ID 3ð MOSS CHECK ð9 3ð Flag error C 31 CCU 31 32 Alert indicator 32 33 IPL CHECK ðF1B 33 Req 34 36 X71 MSA displ 34 FCN 37 39 X72 MSA displ 35 Serv 4ð 42 IAR Panel old 43 45 WKR1 36 Req 46 48 WKR2 37 FCN 49 51 WKR3 38 Serv 52 54 WKR4 39 86 Hexadecimal codes 55 57 WKR5 87 88 CDF RC 58 6ð WKR6 89 9ð ECB DISC 61 63 WKR7 MIOC 64 65 X7E ...

Page 528: ...eaning Byte Meaning 1 27 Header 1 27 Header 28 29 TYPE ID 28 29 TYPE ID 3ð DUMP 3ð 37 OC1 31 TRACE 38 45 OC2 32 CA 46 53 CCUF 33 CCU 54 61 CCUB 34 Unused 62 77 IORB 82 93 PLIST Format foM19 Format foM21 ID ð6 ID 2ð MOSS Check ð8 Byte Meaning EXT ð7 1 27 Header Byte Meaning 28 29 TYPE ID 3ð MOSS check 1 27 Header 31 ORIGI 28 29 TYPE ID 32 Function 3ð MOSS CHECK 33 SERV 31 EXT 34 CCU 32 CCU 35 STATU...

Page 529: ...re may be 35 CCU default more than 35 3745 mode three BERs Format foM24 Format foM25 IDs 24 to 29 37 ID 3ð Byte Meaning Byte Meaning 1 27 Header 1 27 Header 28 29 TYPE ID 28 29 TYPE ID 3ð CA 3ð 31 FRU GROUP Format foM27 Format foM27a ID 32 ID ðA Byte Meaning Byte Meaning 1 27 Header 1 27 Header 28 29 TYPE ID 28 29 TYPE ID 3ð 33 PLIST 3ð Error code FF 34 37 PRB 31 Error extension 39 DATA 32 ELA num...

Page 530: ...T 37 38 TIC 2 4ð 41 2K blk FINAL 39 42 Unused 42 STOP CMD CNT 43 44 MOSS error status 45 46 Lvl 1 error status 47 48 TIC CTL register 49 51 X 76 Format foM29b Format foM3ð ID ð7 ID 15 EXT ð1 ð2 ð3 ð4 ð5 Byte Meaning Byte Meaning 1 27 Header 1 27 Header 28 29 TYPE ID 28 29 TYPE ID 3ð ERROR 3ð 37 OC1 31 ERROR EXT 38 45 OC2 32 TRA number 46 53 CCUF 33 34 TRA address 54 61 CCUB 35 TIC number 62 77 IOR...

Page 531: ...T 39 M STAT Format foM34 Format foM35 ID ð6 ID ð6 MOSS Check 13 MOSS Check 14 Byte Meaning Byte Meaning 1 27 Header 1 27 Header 28 29 TYPE ID 28 29 TYPE ID 3ð MOSS CHECK 3ð MOSS CHECK 31 CCU 31 CCU 32 35 LOAD MODULE name 32 35 LOAD MODULE name 36 4ð TIMED IPL DATE TIME 36 4ð TIMED IPL DATE TIME 41 45 REFERENCE DATE TIME 41 45 REFERENCE DATE TIME 46 MOSS CANCEL ORIGIN Figure 11 16 Part 8 of 11 MOSS...

Page 532: ...ID 28 29 TYPE ID 3ð TA 3ð TA 31 TD 31 TD 32 CCU 32 CCU 33 36 SLID 33 Origin Format foM4ð Format fo41 ID Að ID A1 Byte Meaning Byte Meaning 1 27 Header 1 27 Header 28 29 TYPE ID 28 29 TYPE ID 3ð 31 Error code 3ð Reason 32 34 Panel code 31 33 Panel code 35 37 IML request 38 MOSS MOSS E model 39 42 DIAG status Format foM42 ID A2 Byte Meaning 1 27 Header 28 29 TYPE ID 3ð 32 Old panel code Figure 11 16...

Page 533: ...7 Receive counter 58 Transmit error 59 Receive error 6ð 61 T1 expired ID 2C 62 Received command 63 Sent command Byte Meaning 64 Primary state 65 Secondary state 1 27 Header 66 Station VS 28 29 TYPE ID 67 Station VR 3ð 31 Completion code 68 Station VA 32 35 CPN MAC counters 36 CCU ID 69 Line error 37 6ð Reference code 7ð Internal error 71 Burst errors 72 ARI FCI error 73 Abort delimiter Format foM4...

Page 534: ...yte Meaning 1 27 Header 28 29 TYPE ID 3ð IML origine 31 32 Low address 33 34 High address 35 Adapter address Figure 11 16 Part 11 of 11 MOSS BER Type 01 Formats 11 122 IBM 3745 Models 130 150 160 170 and 17A Hardware Maintenance Reference ...

Page 535: ...IFT SECT hhhh ROUTINE hh ADT NBR hh LINE NBR hh F1 END F2 MENU2 F3 ALARM F4 SUMMARY F5 LIST F7 PREVIOUS F8 NEXT á ñ Diagnostics BER Type 03 ID 03 Format foD2 see page 11 124 à ð ELD DETAIL SEL hhhh FLAG hh DATE dd dd TIME dd dd TYPE ð3 ID ð3 ERROR DESCRIPTION REFER CODE IN CHAR CCCCCCCC ERC hhhh RAC hhhh ERROR BIT hhhh ADT NBR hh LINE NBR hh MUX NBR hh CCU ATT hh IFT SECT hhhh ROUTINE hh F1 END F2...

Page 536: ...up number 3ð 33 Unused 31 32 IFT section routine 34 35 Error ref code 33 Adapter seq number 36 37 RAC code 34 Adapter line addr 38 45 Unused 46 47 Error bit 48 61 Unused 62 Adapter seq number 63 Line address Format foD3 64 MUX Id 65 CCU attached 66 189 Unused 19ð IFT IDs ð4 and ð5 191 Section 192 Routine number Byte Meaning 1 27 Header 28 29 Type ID 3ð 43 Unused 44 45 RAC 46 61 Unused 62 Adapter s...

Page 537: ...9 End of IML data due to an unexpected event 3ð Microcode error Power dump AB AB 31 Set time of day 35 Battery changed Perform a POS and a MOSS IML NO A9 36 Change battery A5 A5 Figure 11 18 Power Subsystem BER Type 04 Summary Note The description of the events does not necessarily match the alarm mes sages listed in the Problem Determination Guide Power BER Type 04 Detailed BER Display Power BER ...

Page 538: ... of error according to the next list ID 20 Power control detected error on MOSS reset ID 21 Power control detected error on MMIO ID 22 Power control detected error on RPO signal ID 23 Power control detected error on CCU reset One of those BER is generated when the corresponding lines is found every time clamped to the same level Power BER Type 04 IDs 28 29 Format foP2 see page 11 132 à ð ELD DETAI...

Page 539: ...Description Field name Meaning Refer to AFD Not used BUS ID Not used CCU Value is 00 except in case of case of RPO hh 01 for CCUA Control Mode See OLD and NEW Page 11 128 ECB Event control block ERR Microcode error Page 11 128 IML IPL Source of IML IPL Cause of IML IPL Reason of power OFF Page 11 128 Page 11 128 Page 11 128 Install Type MPW power logic card state Page 11 128 IOIRV I O interrupt re...

Page 540: ...d interrupt Invalid asynchronous event Not used Power dump requested REASON 01 02 03 04 05 06 08 09 1A Last power OFF reason Power OFF from host in host mode power hold signal inactive AC failure Remote power OFF in network mode Power OFF from panel in local mode Power OFF from EPO switch Air flow detector failure Overcurrent problem on a power block Power supply problem on a power block MOSS powe...

Page 541: ...cked 83 PCC Invalid power ON reset dump stacked 84 PCC Invalid interrupt level 0 dump stacked 85 PCC Invalid interrupt level 1 dump stacked 86 PCC Invalid interrupt level 2 dump stacked 11 MOSS Power microcode error 12 MOSS PCC ckeck bad return 20 Operator Manual request via power services Table 11 51 Page 1 of 2 BER 04 REQ RESP Table REQ RESP OK RESP KO Meaning 01 42 C2 Start diskette 02 43 C3 St...

Page 542: ...POWER BER Table 11 51 Page 2 of 2 BER 04 REQ RESP Table REQ RESP OK RESP KO Meaning 22 7F FF Display function code 11 130 IBM 3745 Models 130 150 160 170 and 17A Hardware Maintenance Reference ...

Page 543: ...11 52 BER 04 RESP Table When REQ 00 RESP Meaning 00 to 05 Unused 06 Air flow fault 08 Overcurrent fault 09 PS fault 0D Local request 0E Force local 0F Battery KO 11 Power control mode change 12 Panel KO 13 AC failure 14 Invalid AC failure 15 MPWA KO 16 Remote power OFF 18 Battery OK 19 Problem on CCU reset 1A Problem detected on MOSS reset 1B MMIO errors Chapter 11 Error Logging 11 131 ...

Page 544: ...Airflow fault on 37 BUS ID each tower 38 Adapter 1 39 Adapter 2 4ð RPO 41 CCU Format foP4 ID ðA only ID 31 42 Old control 43 New control Byte Meaning 44 Tower ID for airflow fault 1 27 Header 28 29 TYPE ID 3ð 32 Time SS MM HH in Hex 33 Day of week 34 36 Date day month year Format foP3 Format foP5 ID 3ð IDs 17 35 36 Byte Meaning Byte Meaning 1 27 Header 1 27 Header 28 29 TYPE ID 28 29 TYPE ID 3ð IO...

Page 545: ... Portx Command Rejected by Adapter Microcode Adapter LVL1 with LVL1 Summary Register X7E 2000 IOC 1 with Adapter Status Register Error Status Type 3 non Hardstop or LAS B 1000 00u0 10xx xxxz as command reject on line interface address b xxxxxz where x x reflects the relative line address and z gives the interface side Xmit or Rcv When u 1 this indicates a command reject for command on command Port...

Page 546: ... 1 AIO CCW register X75H or X75L B 1nnn n000 where nnnn from 0 to 15 represents the IOC relative adapter number adapter which was per forming the AIO ELA µ code retry No No 93 ELAyy AIO Invalid CSCW threshold Adapter Down flag is On ELA down 38 38 94 ELAyy Portx Cycle Steal Error on Set Mode Adapter LVL1 with LVL1 Summary Register X7E 2000 IOC 1 Adapter Status Register Error Status Type 3 non Hard...

Page 547: ...rror on GLID threshold ELA down 34 34 9D ELAyy Adapter Microcode detected error Adapter LVL1 with LVL1 Summary Register X7E 2000 IOC 1 with Adapter Status Reg ister Error Status Type 3 non Hardstop or LAS 8800 Microcode Check then NCP reads the adapter Mcode Check TA1 31 which gives the CSECT and checker number This last data overwrites the previous LAS contents which is then not seen in BER displ...

Page 548: ...x DMSW DMA reported error Adapter LVL2 PSA LCS Line Control Status DC SCTL DMA SWDM error and PSA HELCS High byte of extended LCS 06 16 port down 3C 3C A9 ELAyy Portx DMSW DMA Parity Check or Time Out Adapter LVL2 PSA LCS Line Control Status DC SCTL DMA SWDM error and PSA HELCS High byte of extended LCS 08 18 28 Port down 3C 3C AA ELAyy Portx EAC DMA Interface Error Adapter LVL2 PSA LCS Line Contr...

Page 549: ...hhh LAR hhhhhhhh LAS hhhh X76U hhhh ETA hhhh SWA hhhh IAR hhhhhh TA hhhhh TD hhhh IOB LXB hhhhhhhh hhhhhhhh hhhhhhhh hhhhhhhh hhhhhhhh hhhhhhhh hhhhhhhh hhhhhhhh hhhhhhhh CCB hhhhhhhh hhhhhhhh hhhhhhhh hhhhhhhh hhhhhhhh hhhhhhhh hhhhhhhh hhhhhhhh hhhhhhhh hhhhhhhh hhhhhhhh hhhhhhhh hhhhhhhh hhhhhhhh hhhhhhhh hhhhhhhh AXB hhhhhhhh hhhhhhhh hhhhhhhh hhhhhhhh hhhhhhhh hhhhhhhh hhhhhhhh hhhh hh SCB hh...

Page 550: ... MENU2 F3 ALARM F4 SUMMARY F5 LIST F7 PREVIOUS F8 NEXT á ñ ESS BER Type 08 ID 26 A2 A3 A4 A5 A6 A7 A8 A9 AA Format foE5 see page 11 144 Program level 2 generates one of these BERs when a scanner internal error or a transient line error is detected à ð ELD DETAIL SEL hhhh FLAG hh DATE dd dd TIME dd dd TYPE ð8 ID hh LOST ddd CP ABEND hhhh ERROR DESCRIPTION REFER CODE IN CHAR CCCCCCCC F bbbbbbbb TA h...

Page 551: ...BYTEð hh TD BYTE1 hh BFLAG hhhh TDREFLECT hhhh XMTTOT hhhh hhhh RCVTOT hhhh hhhh XMTERR hhhh hhhh RCVERR hhhh hhhh EXCSCLSN hhhh hhhh LATECSLN hhhh hhhh RCVCNGST hhhh hhhh CRCERR hhhh hhhh FRAMERR hhhh hhhh RSIZERR hhhh hhhh XMTDEF hhhh hhhh ONECLSN hhhh hhhh MULTCLSN hhhh hhhh F1 END F2 MENU2 F3 ALARM F4 SUMMARY F5 LIST F7 PREVIOUS F8 NEXT á ñ BFLAG BER flag 40 RCVERR reached its threshold 80 XMT...

Page 552: ...ive frame does not end on a byte boundary RSIZERR A Receive Size Error occurs when a receive frame is longer than the Ethernet allowed maximum frame size of 1518 bytes XMTDEF The Transmit Deferred Counter includes the number of frames for which the initial transmission of the frame was deferred because carrier was sensed on the Ethernet ONECLSN The One Collision Counter includes the number of time...

Page 553: ...P IOB LXB X 24 bytes of LXB for SDLC lines or IOB for BSC SS lines control blocks This area is padded with X FF for PEP CCB X 40 bytes of data from the CCB control block If PEP the fields are CCBL2 through CCBPOLL inclusive If PEP the fields are CCBTROPT through CCBXPTR inclusive AXB ACB TRACE X E bytes of data from the AXB control block from AXBFCTL through AXB X 15 ACB trace area For PEP this ar...

Page 554: ... Table 11 54 Page 2 of 2 ESS BER Type 08 Field Description Field Name Meaning Refer to X74 X 74 LAR bytes See CSn and PORTnn page 2 26 X75 X 75 Cycle steal control word register page 2 26 X76 X 76 IOC error summary register page 2 26 X76U X 76 Cause of error not found PIO to read error reg ister failed page 2 26 X79 X 79 Interrupt level page 2 26 X7E X 7E CCU level 1 interrupt page 2 26 X7F X 7F I...

Page 555: ...47 5ð SPR 49 5ð Unused 51 Flag 51 Flag 52 Unused 52 Unused 53 54 SWA 53 54 SWA 55 58 LAR 55 INTLVL 56 58 IAR 59 6ð TA 61 62 TD 63 66 Unused 67 1ð2 IOB LXB 1ð3 166 CCB 167 198 AXB 199 215 SCB 216 Unused 217 244 PSA Format foE3 ID 1E 95 96 99 9A 9B 9D Byte Meaning 1 27 Header 28 29 TYPE ID 3ð LOST 31 32 Abend 33 34 X7E 35 36 X76 37 ADNO 38 42 Unused 43 44 LAS 45 46 X76U 47 5ð Unused 51 F 52 TSS Flag...

Page 556: ... 218 Count Only for A2 A4 and AB Format foE6 Format foE7 ID 94 1C ID B7 Byte Meaning Byte Meaning 1 27 Header 1 27 Header 28 29 TYPE ID 28 29 TYPE ID 3ð LOST 3ð LOST 31 32 Abend 31 32 Abend 33 F 33 TA Byte ð 34 Interrupt level 1 34 TD Byte 1 35 36 LNVT 35 36 BFLAG 37 52 PSA 37 38 TDREFLECT 53 SCF 39 42 XMTTOT 54 LSTAT 43 46 RCVTOT 55 56 LAS 47 5ð XMTERR 57 CR1 51 54 RCVERR 58 CR2 55 58 EXCSCLSN 59...

Page 557: ...nd GES IOH TA third GES IOH TD CBA down E4 E4 13 Cmd Reject Invalid Adapter Address X7E 2000 IOC 1 with CBA 1 or 0200 IOC 2 with CBA 2 CBA LVL1 with first GES X 2302 second GES IOH TA third GES IOH TD None EB EB 14 Cmd Reject Invalid Line Address X7E 2000 IOC 1 with CBA 1 or 0200 IOC 2 with CBA 2 CBA LVL1 with first GES X 2402 second GES IOH TA third GES IOH TD None F1 F1 15 Cmd Reject No prior St...

Page 558: ... NPSA parameter error Diagnostic code 40 for NPSA Invalid command Diagnostic code 41 for invalid NDPSA pointer Abnormal request reason code C003 for NPSA Error Invalid Halt cause code Line down No but NCP alert F2 31 NDPSA parameter error Diagnostic Code 10 for NDPSA invalid receive initial Diagnostic Code 15 for Invalid NDPSA chain pointer Diagnostic Code 16 for Invalid NDPSA buffer pointer Line ...

Page 559: ...h CBA 2 None No No 96 SAP to MOSS E connection lost X7E 2000 IOC 1 with CBA 1 or 0200 IOC 2 with CBA 2 CBA LVL1 with GES 1st X 1300 None F7 F7 97 IOC PIO Error LVL1 entered after NCP IOH instruction due to X7E 0100 IOC 1 CBA 1 or 0001 IOC 2 CBA 2 and X76 x8 or x4 NCP retry No No 98 IOC PIO Error threshold Identical to BER 09 97 CBA down E6 E6 99 Adapter LVL1 Invalid Error Status X7E 2000 IOC 1 wit...

Page 560: ... command No answer received time out on Execute Request but following Halt has been completed successfully Halt Cause Code 8401 Line down No but NCP alert F3 B1 Line timeout on halt command No answer received time out on Execute Request and on following Halt command None No No B1 Adapter timeout on halt command No answer received time out on Execute Request and on following Halt command CBA down E...

Page 561: ...hhh hhhhhhhh hhhhhhhh hhhhhhhh 1ST NDPSA hhhhhhhh hhhhhhhh hhhhhhhh hhhhhhhh hhhhhhhh hhhhhhhh hhhhhhhh hhhhhhhh NACBWQH hhhh hhhh NACBLCQH hhhh hhhh NACB1HCC hhhh NACBFLAG hh NACBERPF hh PAGE 1 OF 2 F1 END F2 MENU2 F3 ALARM F4 SUMMARY F5 LIST F7 PREVIOUS F8 NEXT á ñ à ð ELD DETAIL SEL hhh FLAG hh DATE dd dd TIME dd dd TYPE ð9 ID hh ERROR DESCRIPTION REFER CODE IN CHAR CCCCCCCC X LXB hhhhhhhh hhhh...

Page 562: ...hhh hhhhhhhh hhhhhhhh hhhhhhhh hhhhhhhh hhhhhhhh hhhhhhhh hhhhhhhh NACBWQH hhhh hhhh NACBLCQH hhhh hhhh NACB1HCC hhhh NACBFLAG hh NACBERPF hh PAGE 1 OF 2 F1 END F2 MENU2 F3 ALARM F4 SUMMARY F5 LIST F7 PREVIOUS F8 NEXT á ñ à ð ELD DETAIL SEL hhh FLAG hh DATE dd dd TIME dd dd TYPE ð9 ID hh ERROR DESCRIPTION REFER CODE IN CHAR CCCCCCCC X LXB hhhhhhhh hhhhhhhh hhhhhhhh hhhhhhhh hhhhhhhh hhhhhhhh hhhhh...

Page 563: ...hhh hhhhhhhh hhhhhhhh hhhh SLID hhhh hhhh NACBFLAG hh NACBERPF hh NACBWQH hhhh hhhh NACBFLCQH hhhh hhhh NACB1HCC hhhh PAGE 1 OF 2 F1 END F2 MENU2 F3 ALARM F4 SUMMARY F5 LIST F7 PREVIOUS F8 NEXT á ñ à ð ELD DETAIL SEL hhh FLAG hh DATE dd dd TIME dd dd TYPE ð9 ID hh ERROR DESCRIPTION REFER CODE IN CHAR CCCCCCCC R LXB hhhhhhhh hhhhhhhh hhhhhhhh hhhhhhhh hhhhhhhh hhhhhhhh hhhhhhhh hhhhhhhh hhhhhhhh X ...

Page 564: ... à ð ELD DETAIL SEL hhh FLAG hh DATE dd dd TIME dd dd TYPE ð9 ID hh ERROR DESCRIPTION REFER CODE IN CHAR CCCCCCCC TRACE PT2 CCTSTATE CCTSNPM CCTRTT CCTOFLAG CCTBAR CCTBKTMR LTVTSTAT hh hh hh hh hh hh hh AITTYPE hh PAGE 2 OF 2 F1 END F2 MENU2 F3 ALARM F4 SUMMARY F5 LIST F7 PREVIOUS F8 NEXT á ñ 3746 900 BER Type 9 ID 35 Format foS5 see page 11 161 à ð ELD DETAIL SEL hhh FLAG hh DATE dd dd TIME dd dd...

Page 565: ...h hhhh NACBFLAG hh NACBRTYP hh LACBFLAG hh R LXBSTFLD hh DATA hhhh hhhh LKEFMT hh AITTYPE hh F1 END F2 MENU2 F3 ALARM F4 SUMMARY F5 LIST F7 PREVIOUS F8 NEXT á ñ 3746 900 BER Type 9 ID A1 Format foS7 see page 11 162 à ð ELD DETAIL SEL hhh FLAG hh DATE dd dd TIME dd dd TYPE ð9 ID hh ERROR DESCRIPTION REFER CODE IN CHAR CCCCCCCC NPSA PARM hhhhhhhh hhhhhhhh hhhhhhhh hhhhhhhh NPSA STAT hhhhhhhh hhhhhhh...

Page 566: ...D hh ERROR DESCRIPTION REFER CODE IN CHAR CCCCCCCC AITADNO hh AITTYPE hh AITCONF hh AITSTAT hh AITPROT hhhh LKEFMT hh TRACE PT1 CCTSTATE CCTSNPM CCTRTT CCTOFLAG CCTBAR CCTBKTMR LTVTSTAT hh hh hh hh hhhh hhhh hh TRACE PT2 CCTSTATE CCTSNPM CCTRTT CCTOFLAG CCTBAR CCTBKTMR LTVTSTAT hh hh hh hh hhhh hhhh hh PAGE 2 OF 2 F1 END F2 MENU2 F3 ALARM F4 SUMMARY F5 LIST F7 PREVIOUS F8 NEXT á ñ 3746 900 BER Typ...

Page 567: ...hh LNVT SEG ADDRESS hhhhhhhh F1 END F2 MENU2 F3 ALARM F4 SUMMARY F5 LIST F7 PREVIOUS F8 NEXT á ñ 3746 900 BER Type 9 ID 1E Format foS11 see page 11 163 à ð ELD DETAIL SEL hhh FLAG hh DATE dd dd TIME dd dd TYPE ð9 ID hh ERROR DESCRIPTION REFER CODE IN CHAR CCCCCCCC X7E hhhh LAR hhhh hhhh INTLVL hh IAR hhhhhh X76 hhhh AITADNO hh AITTYPE hh AITCONF hh AITSTAT hh AITPROT hhhh L1BPIO76 hhhh L1BIOHTA hh...

Page 568: ...r of times the BER appeared GES Get error status page 11 157 IAR IAR of interrupt level page 2 42 INTLVL Interrupt level LAR Lagging Address Register X 74 page 2 42 LKEFMT Functional group page 11 158 L1BERFLG Box event record flags page 11 158 L1BIOHTA TA IOHI image TA data register TA hhhh means data bytes 0 and 1 page 3 36 L1BIOHTD TD IOHI image TD data adapter specific bytes TD hhhh means data...

Page 569: ...from the line adapter when disconnected IOH instruction to line adapter failed twice Unused Line adapter down due to line adapter LVL1 interrupt Unused Line adapter down due to exceeding incident limit Line adapter down due to MOSS command Unused Channel adapter status indicator Channel adapter active for NCP Channel adapter active for EP Channel adapter active for programmed resource Channel adap...

Page 570: ...ent record flags x 0 Control program is EP x 1 Control program is NCP or PEP Adapter down Control program put adapter down Redrive has been disabled NCP only or error on invalid ESC EP only MOSS CACM timeout detected 3745 only Error on get error status CA is being disabled IOH or IOHI on level 1 failed twice L1XGESFG 1 1 1 1 x x x x Invalid GES indicators flag byte Invalid GES error category Inval...

Page 571: ...4 L1BIOHTA 55 56 L1BIOHTD 55 56 L1BIOHTD 57 L1XGESFG 57 L1XGESFG 58 L1BERFLG 58 L1BERFLG 59 6ð L1XSWADE 59 6ð L1XSWADE 61 62 L1BPOHTA 61 62 L1BPOHTA 63 94 NPSA 63 94 LPSA 95 126 NDPSA 95 126 NDPSA 127 13ð NACBWQH 127 13ð NACBWQH 131 134 NACBLCQH 131 134 NACBLCQH 135 136 NACB1HCC 135 136 NACB1HCC 137 NACBFLAG 137 NACBFLAG 138 NACBERPF 138 NACBERPF 139 174 X LXB 139 174 X LXB 175 176 X CCBSTAT1 175 ...

Page 572: ...FLAG 153 NACBFLAG 154 NACBERPF 154 NACBRTYP 155 158 NACBWQH 155 LACBFLAG 159 162 NACBLCQH 156 R LXBSTFLD 163 164 NACB1HCC 157 PT1 CCTSTATE 165 2ðð R LXB 158 PT1 CCTSNPM 2ð1 2ð2 X CCBSTAT1 159 PT1 CCTRTT 2ð3 2ð4 X CCBEND1 16ð PT1 CCTOFLAG 2ð5 2ð6 X CCBBAR 161 162 PT1 CCTBAR 2ð7 X CCBCTL 163 164 PT1 CCTBKTMR 2ð8 X ATTECTL 165 PT1 LTVTSTAT 2ð9 24ð X ATT 166 Unused 241 242 SSBSSCF CUBBSCF 167 PT2 CCTS...

Page 573: ...FLAG 1ð1 NACBFLAG 1ð2 NACBRTYP 1ð2 NACBRTYP 1ð3 LACBFLAG 1ð3 LACBFLAG 1ð4 R LXBSTFLD 1ð4 R LXBSTFLD 1ð5 PT1 CCTSTATE 1ð5 1ð8 DATA 1ð6 PT1 CCTSNPM 1ð9 LKEFNT 1ð7 PT1 CCTRTT 11ð AITTYPE 1ð8 PT1 CCTOFLAG 111 112 Repetit BER count 1ð9 11ð PT1 CCTBAR 111 112 PT1 CCTBKTMR 113 PT1 LTVTSTAT 114 Unused 115 PT2 CCTSTATE 116 PT2 CCTSNPM 117 PT2 CCTRTT 118 PT2 CCTOFLAG 119 12ð PT2 CCTBAR 121 122 PT2 CCTBKTMR ...

Page 574: ...1HCC 97 132 R LXB 133 134 X CCBSTAT1 135 136 X CCBEND1 137 138 X CCBBAR 139 X CCBCTL 14ð X ATTECTL 141 172 X ATT 173 AITADNO 174 AITTYPE 175 AITCONF 176 AITSTAT 177 178 AITPROT 179 LKEFMT 18ð Unused 181 PT1 CCTSTATE 182 PT1 CCTSNPM 183 PT1 CCTRTT 184 PT1 CCTOFLAG 185 186 PT1 CCTBAR 187 188 PT1 CCTBKTMR 189 PT1 LTVTSTAT 19ð Unused 191 PT2 CCTSTATE 192 PT2 CCTSNPM 193 PT2 CCTRTT 194 PT2 CCTOFLAG 195...

Page 575: ...IO76 53 54 L1BIOHTA 53 54 L1BIOHTA 55 56 L1BIOHTD 55 56 L1BIOHTD 57 L1XGESFG 57 L1XGESFG 58 L1BERFLG 58 L1BERFLG 59 6ð L1XSWADE 59 6ð L1XSWADE 61 62 L1BPOHTA 61 62 L1BPOHTA 63 66 CDF E ID 12 only 63 74 GESs 67 78 GESs 75 78 LNVT SEG ADDRESS Format foS11 ID 1E Bytes Meaning 1 27 Header 28 29 TYPE ID 3ð LOST 31 32 Abend 33 34 X7E 35 38 LAR 39 INTLVL 4ð 42 IAR 43 44 X76 45 AITADNO 46 AITTYPE 47 AITCO...

Page 576: ...e IPL NO NO 1C 0914 Output sequence issued in error to CA X 0D bit 1 0 ON NCP re IPL NO NO 1E 0913 Invalid IOH IOHI output to CA output X 0D X 0E or X 0F NCP re IPL NO NO 1F 0913 Invalid IOH IOHI output to CA hardware detected X 7E bit 0 5 ON NCP re IPL NO NO 34 091F Level 3 IPL configuration check Stacked status cleared by initial select for the 1st time or transfer of final status but not on the...

Page 577: ...lved AIO Unresolved adapter error PIO error on a CA NO NO 86 917 919 91A CA not operative Unresolved AIO Unresolved adapter error PIO error on a CA NO NO 87 917 919 91A Interrupt from a disable CA Unresolved AIO Unresolved adapter error PIO error on a CA NO NO 88 917 919 91A Unexpected level 1 in concurrent maintenance Unresolved AIO Unresolved adapter error PIO error on a CA NO NO 89 917 919 91A ...

Page 578: ...d active X 7E bit 0 5 or 1 5 ON NCP retry NO NO 94 0921 Level 1 from a CA not generated active limit threshold NCP re IPL NO NO 96 0 Channel bus IN check X 0D bit 1 3 or 1 5 ON NCP retry NO NO 96 0 Channel bus IN check limit threshold CA down 50 50 96 Channel bus IN check last CA no INN all CAs have been disabled NCP re IPL NO 40 97 0 PIO error Input or output IOH failed X 76 bit 0 4 ON for IOC1 t...

Page 579: ...evel 1 abort ADP recovery NCP re IPL NO NO 9D 0 CA microcode detected error X 0D bit 0 1 ON Origin found in X 60 CA down 51 51 9E 0 Unresolved error on CA level 1 CA register X 0D did not specify any adapter error bit See Specific Mechanism page 11 12 NCP retry NO NO 9E 0 Unresolved error on CA level 1 limit threshold CA down 50 50 9E Unresolved error on CA level 1 last CA no INN All CAs have been...

Page 580: ...r installed nor attached to that CCU NCP re IPL NO NO B9 0 Channel media device level error NCP retry NO NO BA 091E CA level 3 interrupt but the CA is not operational NCP re IPL NO NO BB CA level 3 from a CA that is CACM disconnect MOSS cancel CACM and reset CA NO NO BC CA level 3 from a CA with install in progress MOSS cancel CACM and reset CA NO NO BD 091E CA level 3 from a CA ERP inoperative NC...

Page 581: ...X3 hhhh X4 hhhh X5 hhhh X6 hhhh X7 hhhh XB hhhh XC hhhh XD hhhh XE hhhh XF hhhh F1 END F2 MENU2 F3 ALARM F4 SUMMARY F5 LIST F7 PREVIOUS F8 NEXT á ñ CA BER Type 10 IDs 14 16 91 9A Format foC2 see page 11 176 Program level 1 generates one of the following BERs when an error occurs during an AIO operation with a channel à ð ELD DETAIL SEL hhhh FLAG hh DATE dd dd TIME dd dd TYPE 1ð ID hh LOST ddd CP A...

Page 582: ... XF hhhh F1 END F2 MENU2 F3 ALARM F4 SUMMARY F5 LIST F7 PREVIOUS F8 NEXT á ñ CA BER Type 10 IDs 34 35 B1 B2 B5 B6 BD BE Format foC4 see page 11 177 Program level 3 generates one of the following BERs when a CA request at level 3 remains unresolved à ð ELD DETAIL SEL hhhh FLAG hh DATE dd dd TIME dd dd TYPE 1ð ID hh LOST ddd CP ABEND hhhh ERROR DESCRIPTION REFER CODE IN CHAR CCCCCCCC CAVT bbbbbbbb X...

Page 583: ...gram level 3 generates one of the following BERs when a CA request at level 3 remains unresolved à ð ELD DETAIL SEL hhhh FLAG hh DATE dd dd TIME dd dd TYPE 1ð ID hh LOST ddd CP ABEND hhhh ERROR DESCRIPTION REFER CODE IN CHAR CCCCCCCC F bbbbbbbb X7E hhhh X76 hhhh ADNO hh LAR hhhhhhhh X76U hhhh TA hhhh SWA hhhh XD hhhh XE hhhh XF hhhh CAVT bbbbbbbb CCU INPUT X57 hhhh CCU OUTPUT X57 hhhh F1 END F2 ME...

Page 584: ...h LOST ddd CP ABEND hhhh ERROR DESCRIPTION REFER CODE IN CHAR CCCCCCCC CAVT bbbbbbbb X77 hhhh X7F hhhh TA hh STATUS hhhh Xð hhhh X2 hhhh XF hhhh X6 hhhh CMD hh CABSENSE hh SENSE 1 hh SENSE 2 hh ABORT REASON hh DATA REASON hh CMD REJ REASON hh F1 END F2 MENU2 F3 ALARM F4 SUMMARY F5 LIST F7 PREVIOUS F8 NEXT á ñ 11 172 IBM 3745 Models 130 150 160 170 and 17A Hardware Maintenance Reference ...

Page 585: ... byte indicates a byte expansion follows I First two bytes of instruction IAR IAR of interrupt level page 2 42 LAR Lagging Address Register X 74 page 2 42 SENSE 1 Extended sense byte 1 page 11 174 SENSE 2 Extended sense byte 2 Unused STAT CA Reg X 9 Autoselection chain status STATUS CER channel adapter state page 11 174 SWA Switch adapter error register Unused TA IOHI image TA data registers X 50 ...

Page 586: ...ata Restart reset Discontact control Contact control Sense ID STATUS 8000 4000 2000 1000 0800 0400 0200 0100 CER channel adapter state Attention Status modifier Control unit end Busy Channel end Device end Unit check Unit exception CABSENSE 1 1 1 1 1 1 1 1 CA sense byte Command reject Intervention required Bus out check Equipment check Data check Overrun Not initialized Program abort SENSE 1 1 1 1...

Page 587: ...nd transfer while ANS in progress Bus out check W ANS in progress Equipment check W ANS in progress Inbound transfer data streaming timeout Inbound transfer W ANS in progress Channel stop or HIO received during read Cmd Inbound transfer data streaming timeout XID NEG failed ANS invoqued XID3 received W length error XID3 received W CV22 appened PIU received while not FID4 contacted PIU received whi...

Page 588: ... 45 46 X76U 49 Unused 47 5ð FPR 5ð Adno 51 Flag 51 Flag 52 Unused 52 CAVT 53 54 SWA 53 54 SWA error register 55 68 Unused 55 Unused 69 7ð X5ð 56 58 IAR int level 71 72 X51 59 6ð TA 73 74 X52 61 62 TD 75 122 CAB 63 68 Unused 123 124 CAC 125 15ð CA regs X ð X F 63 64 X8 for 65 66 X9 ID 8ð 9B 67 68 XA 69 7ð X5ð 71 72 X51 73 74 X52 75 122 CAB 123 124 CAC 125 15ð CA Regs X ð X F means that if contents ...

Page 589: ... Unused 39 4ð X1 39 42 LAR 41 42 X2 43 44 Unused 43 44 X3 45 46 X76U 45 46 X4 47 48 TA 47 48 X5 49 5ð Unused 49 5ð X6 51 Flag 51 52 X7 52 Unused 53 54 XB 53 54 SWA 55 56 XC 55 68 Unused 57 58 XF 59 1ð6 CAB CHCB 67 68 X6ð ID 9D 1F 1ð7 1ð8 CAC 1ð9 TA 69 7ð X5ð 11ð Unused F for B5 71 72 X51 111 Flag 73 74 X52 75 76 N A 77 124 CAB 125 126 CAC 127 152 CA Regs X O X F means that if contents are FEFEFE F...

Page 590: ... X ð8 65 66 STAT 67 68 X ðE 69 7ð X ðF 71 74 FPR 75 122 CAB Format foC7 Format foC8 IDs B9 IDs 85 86 88 89 BF Bytes Meaning Bytes Meaning 1 27 Header 1 27 Header 28 29 TYPE ID 28 29 TYPE ID 3ð LOST 3ð LOST 31 32 Abend 31 32 Abend 33 34 X77 33 34 X7E 35 36 X7F 35 36 X76 37 38 STATUS 37 ADNO 39 4ð Xðð 38 CAVT 41 42 Xð2 39 42 LAR 43 TA 43 44 TA 44 CAVT 45 46 76U 45 46 XðF 47 F 47 48 Xð6 48 Unused 49 ...

Page 591: ...gister X76 5800 IOC 1 LAS line adapter status bit 1 7 is On Origin given in error status type 1 of CSP bit 1 7 ON NCP re IPL NO NO 1C 0 Line command reject Error status type 3 of CSP bit 1 0 1 Line down 43 43 1E 0 HSSyy Invalid Output IOH to Adapter Adapter LVL1 with LVL1 Summary Register X7E 2000 IOC 1 with Adapter Status Register Error Status Type 3 non Hardstop or LAS B 1000 000u 0100 0000 as I...

Page 592: ... 0 HSSyy AIO Invalid CSCW IOC Error LVL1 with LVL1 Summary Register X7E 0100 IOC 1 with IOC LVL1 Register X76 2200 IOC 1 AIO CCW register X75H or X75L B 1nnn n000 where nnnn from 0 to 15 represents the IOC relative adapter number adapter which was performing the AIO TSS µcode retry NO NO 93 0 Scanner AIO invalid CSCW limit threshold LSS HSS down 63 63 94 HSSyy Portx Cycle Steal Error on Set Mode A...

Page 593: ...Status Type 3 non Hardstop or LAS B 1iii 0uu0 0000 000v where iii invalid inter rupt level from 0 to 7 and u are checkers raised by Mcode and v by hardware LSS HSS down 63 63 9A 0 Scanner adapter error unresolved First get error status failed but retry was succesful Error status has value at time of failure NCP retry NO NO 9B 0 Interrupt from disconnected scanner Level 1 interrupt presented to NCP...

Page 594: ...0 Internal LIC error reported via level 2 X 77 bit 0 1 ON Line cannot be accessed by configuration LCS DE Line down 43 43 A3 0 Internal FESH error reported via level 2 X 77 bit 0 1 ON Line not accessible a line is already active LCS DE Line down 43 43 A4 0 Time out on any command except F5 F5 command sent to the scanner back up timer in NCP PEP level 3 expired before receiving level 2 from scanner...

Page 595: ... DC ELCS bits 4 5 6 101 Line down 73 73 AB Internal LIC error level 2 LIC5 and LIC6 Line down 43 43 B1 0 Scanner command time out on F5 Command F5 sent to the scanner back up timer in NCP PEP level 3 expired before receiving level 2 from scanner to process it Line down 43 43 Note In case of abend NCP re IPL is performed and the Alarm Alert is generated when IPL is completed Alert is triggered by M...

Page 596: ...occurs during a PIO operation on a scanner à ð ELD DETAIL SEL hhhh FLAG hh DATE dd dd TIME dd dd TYPE 11 ID hh LOST ddd CP ABEND hhhh ERROR DESCRIPTION REF CODE IN CHAR CCCCCCCC F bbbbbbbb X7E hhhh X76 hhhh I hhhh LAR hhhhhhhh LAS hhhh X76U hhhh ETA hhhh SWA hhhh IAR hhhhhh TA hhhhh TD hhhh IOB LXB hhhhhhhh hhhhhhhh hhhhhhhh hhhhhhhh hhhhhhhh hhhhhhhh hhhhhhhh hhhhhhhh hhhhhhhh CCB hhhhhhhh hhhhhh...

Page 597: ...d TYPE 11 ID hh LOST ddd CP ABEND hhhh Error description REFER CODE IN CHAR CCCCCCCC F bbbbbbbb TA hh TD hh NW hhhh IDR hhhh LNVT hhhhhhhh LCS hh PSA hhhh hhhh hhhh hhhh hhhh hhhh hhhh hhhh hhhh hhhh hhhh hhhh hhhh hhhh CNT hhhh OVERRIDE FLAG WITH NEW HEXADECIMAL VALUE F1 END F2 MENU2 F3 ALARM F4 SUMMARY F5 LIST F7 PREVIOUS F8 NEXT á ñ TSS HPTSS BER Type 11 ID B1 Format foT5 see page 11 190 These ...

Page 598: ...NU2 F3 ALARM F4 SUMMARY F5 LIST F7 PREVIOUS F8 NEXT á ñ Note Lost and CP abend fields are displayed when applicable TSS HPTSS BER Type 11 ID 94 1C Format foT6 see page 11 190 Program level 1 generates this BER when a command reject is reported by a scanner on level 1 control program error à ð ELD DETAIL SEL hhhh FLAG hh DATE dd dd TIME dd dd TYPE 11 ID hh LOST ddd CP ABEND hhhh ERROR DESCRIPTION R...

Page 599: ...for PEP BSC SS and BNN lines CNT Repetition count BER flooding Number of times the BER appeared SCF Secondary control field I First two bytes of instruction IAR IAR of interrupt level LCS Line control status Chapter 4 and page 5 31 LINEnn Line number 0 to 31 within the CS in error description line LNVT Line vector table Chapter 4 LOST Lost record count LRC NW Network address NCP or CA number and E...

Page 600: ...s The byte contents of the PSA depend on the current command CCMD Chapter 4 TA IOH IOHI image TA data registers X 50 X 70 TA hh means TA data byte 0 see CSn and LINEnn Chapter 4 TD IOH IOHI image TD data adapter specific bytes TD hh means TD data byte 1 Chapter 4 X3F CSP shared pointer register Page 2 26 X74 X 74 LAR bytes See CSn and LINEnn Page 2 26 X75 X 75 Cycle steal control word register Pag...

Page 601: ...4 X7E 33 34 X7E 35 36 X76 35 36 X76 37 38 X75 37 38 I 39 4ð Unused 39 42 LAR 41 42 ETA 43 44 LAS 43 44 LAS 45 46 X76U 45 46 X76U 47 48 ETA 47 5ð SPR 49 5ð Unused 51 Flag 51 Flag 52 Unused 52 Unused 53 54 SWA 53 54 SWA 55 58 LAR 55 INTLVL 56 58 IAR 59 6ð TA 61 62 TD 63 66 Unused 67 1ð2 IOB LXB 1ð3 166 CCB 167 198 AXB 199 215 SCB 216 Unused 217 244 PSA Figure 11 23 Part 1 of 2 TSS HPTSS BER Formats ...

Page 602: ...nt 183 198 PSA Trace Format foT5 Format foT6 IDs 26 A2 A3 A4 A5 A6 A7 ID 94 1C A8 A9 AA AB B1 Byte Meaning Byte Meaning 1 27 Header 1 27 Header 28 29 TYPE ID 28 29 TYPE ID 3ð LOST 3ð LOST 31 32 Abend 31 32 Abend 33 Flag 33 F 34 Unused 34 Interrupt level 1 35 36 IDR 35 36 LNVT 37 64 PSA 37 52 PSA 65 TA byte ð 53 SCF 66 TD byte 1 54 LSTAT 67 68 NW 55 56 LAS 69 1ð4 IOB LXB 57 CR1 1ð5 168 CCB 58 CR2 1...

Page 603: ...3 ON NCP re IPL NO NO 15 0952 Storage protect I fetch IAR not 0 X 7E bit 1 2 ON NCP re IPL NO NO 16 0953 Storage protect I execution X 7E bit 1 4 ON NCP re IPL NO NO 17 0954 Level 5 branch to storage location 0 IAR 0 NCP re IPL NO NO 18 0955 User non NCP code branch to storage location 0 IAR 0 NCP re IPL NO NO 19 000E Logic error interrupt reason lost Program check in level 1 NCP re IPL NO NO 21 0...

Page 604: ...uest at level 2 remains unresolved à ð ELD DETAIL SEL hhhh FLAG hh DATE dd dd TIME dd dd TYPE hh ID hh LOST ddd CP ABEND hhhh ERROR DESCRIPTION REFER CODE IN CHAR CCCCCCCC X7F hhhh IAR3 hhhhhhhh IAR4 hhhhhhhh F1 END F2 MENU2 F3 ALARM F4 SUMMARY F5 LIST F7 PREVIOUS F8 NEXT á ñ NCP PEP BER Type 12 Field Description Note All values are in hexadecimal notation X 0 to X F Table 11 64 NCP PEP BER Type 1...

Page 605: ...te Meaning Byte Meaning 1 27 Header 1 27 Header 28 29 TYPE ID 28 29 TYPE ID 3ð LOST 3ð LOST 31 32 Abend 31 32 Abend 33 34 X7E 33 34 X7F 35 Unused 35 38 IAR3 36 38 X74 39 42 IAR4 39 X79 byte 1 4ð 42 IAR 43 44 I Figure 11 24 NCP PEP BER Formats Chapter 11 Error Logging 11 193 ...

Page 606: ...nd X 7F bits 0 2 0 6 1 5 and 1 6 ON level 3 raised by MOSS diag user timer or PCI NO NO B1 0974 Unresolved level 3 interrupt limit threshold NCP re IPL NO NO C1 0 Unresolved level 4 interrupt NCP reading out X 7F does not find bits 0 3 0 4 0 7 and 1 7 ON Level 4 interrupt raised by MOSS request SVC MOSS response SVC PCI or SVC NO NO C1 0975 Unresolved level 4 interrupt limit threshold NCP re IPL N...

Page 607: ...IPL is performed and the Alarm Alert is generated when IPL is completed Alert is triggered by MOSS BER ID 06 error code 05 CCU BER Type 13 Detailed BER Display CCU BER Type 13 IDs 32 B1 Format foU1 see page 11 197 BER generated by program level 3 à ð ELD DETAIL SEL hhhh FLAG hh DATE dd dd TIME dd dd TYPE 13 ID hh LOST ddd CP ABEND hhhh ERROR DESCRIPTION REFER CODE IN CHAR CCCCCCCC X77 hhhh X7F hhh...

Page 608: ...escription Field Name Meaning Refer to IAR IAR of interrupt level Chapter 7 MTF Mailbox trace facility RCB Level 4 router control block Chapter 7 X0 X 0 Channel adapter initial selection register Chapter 7 X1 X 1 CA CSCW and subchannel address Chapter 7 X2 X 2 Data status register Chapter 7 X3 X 3 CA ESC subchannel Chapter 7 X4 X 4 CA IOH bytes 1 and 2 Chapter 7 X5 X 5 CA IOH bytes 3 and 4 Chapter...

Page 609: ...X ðF 4ð 42 IAR 63 88 Unused 43 44 X 7D CCU hardcheck 89 9ð TA register 91 92 CCU input X57 45 46 CCU input X57 93 94 CCU output X57 47 48 CCU output X57 95 BER flag 49 BER flag Format foU3 IDs C1 to C6 Byte Meaning 1 27 Header 28 29 TYPE ID 3ð LOST 31 32 CP ABEND 33 34 X 77 35 36 X 7F 37 44 RCB 45 46 NTF trace ident 47 76 mailbox or status 77 78 NTF trace ident 79 1ð8 mailbox or status 1ð9 11ð NTF...

Page 610: ... X 76 bit 0 5 for bus IN parity error X 76 bits 0 0 0 1 0 2 0 3 contain the IOC internal error status at time of error 9A 0990 IOC X Unresolved Adapter LVL1 threshold No adapter identified as raising interrupt level 1 NCP abend NO E3 9C IOC X Unresolved Adapter LVL2 No adapter identified as raising interrupt level 2 None NO NO 9C 0937 IOC X Unresolved Adapter LVL2 threshold No adapter identified a...

Page 611: ...hhh L1BERFLG hh F1 END F2 MENU2 F3 ALARM F4 SUMMARY F5 LIST F7 PREVIOUS F8 NEXT á ñ IOC BER Type 14 Field Description Table 11 68 Page 1 of 2 IOC BER Type 14 Field Description Field Name Meaning Refer to IAR IAR of interrupt level page 2 42 INTLVL Interrupt level LAR Lagging Address Register X 74 page 2 42 L1BERFLG Box event record flags page 11 158 L1BIOHTA L1BPIOTA IOHI image TA data register TA...

Page 612: ... Header 1 27 Header 28 29 TYPE ID 28 29 TYPE ID 3ð Lost 3ð Lost 31 32 Abend 31 32 Abend 33 34 X7E 33 34 X7E 35 38 LAR 35 36 X76 39 INTVL 37 38 X75 4ð 42 IAR 39 42 X74 43 44 X76 43 44 Unused 45 46 L1BIOHTA 45 46 X76U 47 48 L1BIOHTD 47 48 CCU input X57 49 5ð Unused 49 5ð CCU output X57 51 52 L1XSWADE 51 Flag 53 54 Unused 52 Unused 55 56 L1BERFLG 53 54 SWA Format foI3 IDs 9A 9C Byte Meaning 1 27 Head...

Page 613: ...error unresolved limit threshold TRM down 82 93 0 TRM AIO invalid CSCW X 75 bit 0 0 or 1 0 ON X 76 bits 0 2 and 0 6 or 1 2 and 1 6 ON TIC retry NO 93 0 TRM AIO invalid CSCW limit threshold TRM down 82 96 0 TRM disconnect state following request from MOSS X 7E bit 0 2 or 0 6 ON Error status bit 0 7 ON Ext register X 01 bit 5 ON TRM OFF line B9 97 0 TRM PIO error output IOH IOHI X 75 bit 0 0 or 1 0 ...

Page 614: ...M status bit 0 ON TRM status bits 4 5 not 000 TIC retry NO A4 0 DMA or interrupt vector error due to TIC limit threshold TIC down 80 A5 0 DMA or interrupt vector error due to TRM Interrupt level 2 TRM status bit 0 ON TRM status bit 6 ON TIC retry NO A5 0 DMA or interrupt vector error due to TRM limit threshold TRM down 83 A7 0 PIO MMIO error interrupt level 2 TRM status bit 0 ON TRM status bits 1 ...

Page 615: ...ed during the incomplete frame timer TIC down 8C B7 0 Token ring link error not caused by controller hardware TIC down 8E Notes 1 In case of abend NCP re IPL is performed and the Alarm Alert is generated when IPL is completed Alert is triggered by MOSS BER ID 06 error code 05 2 BER ID B2 may generate diferent alerts according to the value of the interrupt register see alerts 8D 84 80 TRSS BER Type...

Page 616: ...s disconnected by MOSS or when an error is exported by a TRM on level 1 à ð ELD DETAIL SEL hhhh FLAG hh DATE dd dd TIME dd dd TYPE 15 ID hh LOST ddd CP ABEND hhhh TRMnn TICn ERROR DESCRIPTION REFER CODE IN CHAR CCCCCCCC F bbbbbbbb X7E hhhh X76U hhhh TRMA hh X76 TRM STATUS1 SWA ERROR REG hhhh bbbbbbbb bbbbbbbb bbbbbbbb bbbbbbbb F1 END F2 MENU2 F3 ALARM F4 SUMMARY F5 LIST F7 PREVIOUS F8 NEXT á ñ TRS...

Page 617: ...eck occurs at open time à ð ELD DETAIL SEL hhhh FLAG hh DATE dd dd TIME dd dd TYPE 15 ID hh LOST ddd CP ABEND hhhh ERROR DESCRIPTION REF CODE IN CHAR CCCCCCCC F bbbbbbbb TA hhhh TICA hh TRM STATUS2 bbbbbbbb bbbbbbbb SSB hhhh bbbbbbbb bbbbbbbb F1 END F2 MENU2 F3 ALARM F4 SUMMARY F5 LIST F7 PREVIOUS F8 NEXT á ñ TRSS BER Type 15 ID B2 Format foR7 see page 11 209 Program level 3 generates the followin...

Page 618: ...NU2 F3 ALARM F4 SUMMARY F5 LIST F7 PREVIOUS F8 NEXT á ñ TRSS BER Type 15 Field Description Table 11 70 Page 1 of 2 TRSS BER Type 15 Field Description Field Name Meaning Refer to TICA TIC internal address 00 01 within the TRM Chapter 6 TRM STAT2 TRA level 2 error status Chapter 6 TRMnn TRM number decimal in error description field This TRM number is derived from field TA for PIO operation for CS er...

Page 619: ...ws TRMA TRM address Chapter 6 I First two bytes of instruction IAR IAR of interrupt level X3F CSP shared pointer register Chapter 4 X74 X 74 LAR bytes Page 2 26 X75 X 75 Cycle steal control word register Page 2 26 X76 X 76 IOC error summary register Page 2 26 X76U X 76 Cause of error not found PIO to read error register failed Page 2 26 X77 X 77 Interrupt request reg adapter level 2 and 3 Page 2 2...

Page 620: ...eactivation from host in progress TRSS BER Type 15 Formats Format foR1 Format foR2 IDs 14 16 91 92 93 IDs 18 97 98 9C Byte Meaning Byte Meaning 1 27 Header 1 27 Header 28 29 TYPE ID 28 29 TYPE ID 3ð LOST 3ð LOST 31 32 Abend 31 32 Abend 33 34 X7E 33 34 X7E 35 36 X76 35 36 X76 37 38 X75 37 38 I 39 4ð Unused 39 42 X74 41 42 ETA 43 44 TRM STATUS1 43 44 TRM STATUS1 45 46 X76U 45 46 X76U 47 48 ETA 47 5ð...

Page 621: ...Header 1 27 Header 28 29 TYPE ID 28 29 TYPE ID 3ð LOST 3ð LOST 31 32 Abend 31 32 Abend 33 F 33 F 34 TICA 34 TICA 35 36 TA data 35 36 TA data 37 38 TRM STATUS2 37 38 TRM STATUS2 39 46 Adapter check 39 42 SSB open status completion Format foR7 Format foR8 IDs B3 to B6 ID B2 Byte Meaning Byte Meaning 1 27 Header 1 27 Header 28 29 TYPE ID 28 29 TYPE ID 3ð LOST 3ð LOST 31 32 Abend 31 32 Abend 33 F 33 F...

Page 622: ...ader 28 29 TYPE ID 3ð LOST 31 32 Abend 33 F 34 TICA 35 36 TA data 37 NTRI Alert number 38 PLM status 39 42 Alert Q3 field Figure 11 27 Part 3 of 3 TRSS BER Formats 11 210 IBM 3745 Models 130 150 160 170 and 17A Hardware Maintenance Reference ...

Page 623: ...ler Card EAC 12 15 CSP Layer 12 16 DMA Manager Layer 12 16 Address PROM Layer 12 16 Bus Interconnection Layer 12 16 Transmit Receive Control Layer 12 17 Serial Conversion and Coding Layer 12 17 Isolation Layer 12 17 Reset EAC 12 17 ELA Command Description 12 18 Set Mode 12 18 Enable 12 19 Disable 12 20 Change 12 21 Transmit Data 12 21 Receive 12 22 Get Counters 12 23 Halt 12 23 Halt Immediate Comm...

Page 624: ...onnection Errors 12 41 EAC Internal Checkers 12 42 Error Status 12 42 Diagnostic Facilities 12 44 Problem Determination Aid 12 45 NCP Buffer Prefix Validity Checking in Receive 12 45 SIT Trace 12 45 12 2 IBM 3745 Models 130 150 160 170 and 17A Hardware Maintenance Reference ...

Page 625: ...The ESS in 3745 Models 130 150 160 and 170 Data Flow Chapter 12 Ethernet Subsystem ESS 12 3 ...

Page 626: ...he ESS in 3745 Model 17A Data Flow For model 17A DMA and IOC buses are connected to the CBC in the 3746 900 This MLA card links the MOSS to the Service Processor through a LAN 12 4 IBM 3745 Models 130 150 160 170 and 17A Hardware Maintenance Reference ...

Page 627: ...P microcode load module see ELA Microcode Description on page 12 11 One Ethernet adapter card the EAC card ELA is installed in HSS positions The ELA interface to the external equipment is a IEEE 802 3 15 pin D type female AUI connector requiring a slide latch on mounting connector The ESS uses the tail gate location of the corresponding HPTSS For board and card locations refer to the Maintenance I...

Page 628: ...pports a maximum of two line addresses With two possible ELAs the maximum number of lines is four Line numbers 1060 through 1063 are dedicated for ELA use The two lines associated with a particular ELA are addressed by the TD1 field of the IOH TD1 bit 6 selects one of the two lines TD1 bit 7 selects either the transmit or receive interface of the line When TD1 bit 7 0 it selects the transmit inter...

Page 629: ...it Data 51 Receive Data 53 Trace 2C Stop trace 2D Halt Fð Halt immediate F1 Dump Control blocks no status F4 Dump Control blocks status F5 Suspend Receive F8 Get Counters 5ð For details on ELA commands see ELA Command Description on page 12 18 Interface or Port Types Up to eight ELAs attaching up to four Ethernet LAN Version 2 or IEEE 802 3 net works operating at 10 Mbps Chapter 12 Ethernet Subsys...

Page 630: ... ELAs 5 CSP EAC 5 Local IOC Bus Area 5 CSP EAC Network 5 TERMD DMA Bus 2 EACs Maximum on Basic Board Only CCU SCTL Main Storage Figure 12 2 ESS Data Flow 12 8 IBM 3745 Models 130 150 160 170 and 17A Hardware Maintenance Reference ...

Page 631: ...me DESTINATION ADDRESS 8 D Only 48 bit addresses are supported by Ethernet V2 SOURCE ADDRESS E 13 Address of the source Ethernet adapter for the frame TYPE 14 15 To identify the higher level protocol that is embedded within the Ethernet V2 frame The types supported by the 3745 Ethernet are X 800 IP X 806 ARP DATA The size of this field can vary from a minimum of 46 bytes to a maximum of 1500 bytes...

Page 632: ...XID frame x BF and Test frame X F3 DATA Variable length field that contains the information portion of the frame The length of the information must be within a range that allows the total size of the IEEE 802 3 frame data to less than the allowed maximum For the 10 megabit 500 meter IEEE 802 3 standard this value is the same as that for Ethernet V2 1500 bytes Note however that the IEEE 802 2 heade...

Page 633: ... the ELA RAM Microcode Initialization of the ELA RAM Microcode Dump of the ELA RAM Control Storage Microcode control blocks ELA Microcode Structure CSP Card The CSP card provides Interconnection to the IOC bus Interconnection to the EAC card JIB processor which includes The CSP ROS Local Store registers Control Storage RAM Ping and Pong buffers External Registers addressing for 32 registers Addres...

Page 634: ...or cycle steal operation operational flag bits TA TD of the command in progress and so on PSA Parameter Status Area There are two PSAs for each line one for each interface transmit and receive The PSAs contain the parameters obtained from the CCU for the command in progress and the Status after the command is complete LCB Line Control Block There is one LCB for each line The LCB contains informati...

Page 635: ...is not used when the EAC is running EAC to CSP The physical interconnection between the EAC and the CSP is identical to that between the FESH and the CSP of the HSS For board and card locations see Maintenance Information Procedures Manual Microcode to EAC The picocode is loaded from the CSP in each layer of the EAC RAM at IML time The EAC to CSP interconnection is activated and controlled via ext...

Page 636: ...s Communication Scanner Processor CSP The ELA CSP hardware is identical to that of the LSS CSP refer to Chapter 4 Transmission Subsystem for details 12 14 IBM 3745 Models 130 150 160 170 and 17A Hardware Maintenance Reference ...

Page 637: ... transmit receive handling of the EAC is functionally organized in layers To CSP CSP Bus Transmit Serial Isolation Layer 5 Intercon Receive Conversion Layer I 5 nection Control and Coding 5 Line 1 n Layer Layer Layer t To DMA e Layer 5 r DMA n Bus a l Address PROM 5 B Layer u s Bus Transmit Serial Isolation RAM Intercon Receive Conversion Layer Data 5 5 nection Control and Coding 5 Line 2 Buffer L...

Page 638: ... data transfer from to CCU main storage to from transmit receive data buffers Address PROM Layer The address PROM contains The 48 bit Universal Ethernet address for line 1 The 48 bit Universal Ethernet address for line 2 The one s complement of each of the above addresses The addresses are read by the picocode and placed in the RAM where they are accessed by the CSP microcode Bus Interconnection L...

Page 639: ...es status to the CSP layer after each transmit receive operation Generates CRC Checks CRC Checks network addresses Synchronizes adapter with network Checks receive frame lengths Serial Conversion and Coding Layer The serial conversion and coding layer Converts from parallel to serial data on transmit Converts from serial to parallel data on receive Converts to from binary from to differential Manc...

Page 640: ... used in filtering of frames being received Set mode must be the first command issued to a line If another command is received before the Set Mode it is rejected and a CCU level 1 interrupt request is raised One exception to this rule exists a Halt Immediate issued before the Set Mode for example when there is no outstanding command will be accepted It will however be ignored as there is no outsta...

Page 641: ...nable command are stacked in the CSP and will be passed to NCP in the ending status of the next command The ESS microcode will run a 10 second timer waiting for the EAC to finish its Enable process If the timer expires an LCS of D0 will be returned as an internal box error because this is a picocode hardware function only CSP Processing 1 Start an Enable timer 2 Initialize the ECA initialization b...

Page 642: ...transmit any packets The line is placed in the disa bled state and an Enable command must be issued before the line can transfer data again A Disable may be issued to the even interface only It will be rejected if issued to the odd interface The ESS microcode will run a 10 second timer waiting for the EAC to finish its Disable process CSP Processing 1 Start the disable timer 2 Issue a Disable comm...

Page 643: ...rrupt request Typical Ending Statuses SCF SES LCS Meaning 44 ðð ðð Change complete ðð ðð D2 Command rejected ðð ðð Seeñ Internal box error ñ Refer to Line Communication Status LCS on page 12 30 for details Transmit Data The Transmit Data Command is used to transmit Ethernet V2 frames IEEE 802 3 frames This command will be rejected if issued to the odd interface The entire frame must be contained i...

Page 644: ...AR C4 ðð ðð Halt executed ñ Refer to Line Communication Status LCS on page 12 30 for details Receive The Receive Command is used to pass the address of the first buffer in a receive data buffer chain to the CSP and to place the CSP in receive mode CSP Processing 1 Get the parameters from the CCU 2 Prepare a receive control word for the EAC containing The buffer count from the PSA The buffer offset...

Page 645: ...the counters in the buffer provided 3 Build an ending status and transfer it to the CCU This status will include the Counter that Overflowed status byte 4 Set a CCU level 2 interrupt request Typical Ending Statuses SCF SES LCS Meaning 4C ðð ðð Counter Data Stored ðð ðð D2 Command rejected ðð ðð Seeñ Internal box error C4 ðð ðð Halt executed ñ Refer to Line Communication Status LCS on page 12 30 fo...

Page 646: ...ld ID The halt will then become the outstanding command CSP Processing 1 Make the halt the outstanding command if there is no other command in process 2 Perform the defined operation 3 Update the status area and transfer it to the CCU 4 Raise a CCU level 2 interrupt Halt Immediate Command The halt immediate Halti command is used to terminate an outstanding command and does not require a CCU level ...

Page 647: ...information between the control program in the CCU and the CSP Information is transferred using cycle steal under control of the CSP The parameter status area is made up of 1 A parameter area 16 bytes long 2 A status area 12 bytes long The parameter area is used to pass to the CSP parameters required in the exe cution of a command The status area is used to pass ending status to the control progra...

Page 648: ...t line or start line initial TD byte 0 is the command to be performed by the scanner and TD1 contains the line interface address Refer to the description of each operation for a definition of the TD fields IOH IOHI Instruction Summary IOH IOHI Description Code ðð Start line ð1 Get line ID 1ð Start line initial 11 Get error status 2ð Set line vector table high 21 Get command reject status 3ð Set li...

Page 649: ...eject Status Get command reject status TA byte 1 X 21 is issued to the CSP after the CCU has received a command reject error status to gather more information about the command reject The CSP responds with a two byte status which identifies the command in process followed by the command that overlapped it There is no default value for TD Set Line Vector Table Low Set line vector table low TA byte ...

Page 650: ... result of this instruction the ELA sets a CCU level 1 interrupt and returns a status that causes NCP to request a scanner dump from MOSS CSP Addressing The CSPs associated with the possible eight ELAs installed in a 3745 are assigned the addresses of the first eight line adapters LA on the LA board 1 TSSB board These addresses are used in the input and output instructions to select individual ELA...

Page 651: ...ffer Pointer 1 3 4 5 6 First Buffer Pointer 2 7 SCF CCMD 8 SES LCS 9 Residual Count ELCS IP Dynamics mode Set Mode A Last Buffer Pointer Last Buffer Pointer B C D E F Figure 12 5 General ELA PSA Layout Status Control Field SCF This byte contains information which describes the progress of the operation being executed Bit ð 1 2 3 4 5 6 7 Meaning x Halt x Service request x Unused x Hardware error LC...

Page 652: ... The ISF LCS bits 0 1 indicates essentially the type of line control that is used The ISF is decoded as follow ISF FSF ð 1 2 3 4 5 6 7 Meaning 1 ð ð Special status 1 1 ð Internal box error 1 1 1 Hardware error Special Status See paragraph Initial Status B 100 Special on page 12 31 for more explanation Internal box error See paragraph Initial Status B 110 Internal Box Error on page 12 31 for more e...

Page 653: ...nsmitter timeout error 1 1 ð ð 1 ð 1 ð Storage error 1 1 ð ð 1 ð 1 1 Transmit overrun 1 1 ð ð 1 1 1 ð Receive buffer error 1 1 ð 1 ð ð ð ð No interrupt from EAC 1 1 ð 1 ð ð 1 ð Command rejected See Note 1 1 1 ð 1 ð 1 ð ð Trace already active 1 1 ð 1 ð 1 1 ð Transmit buffer error 1 1 ð 1 1 ð ð ð Invalid level 2 interrupt 1 1 ð 1 1 ð 1 ð Underflow 1 1 ð 1 1 1 ð ð SCTL DMA DMSW error See Note 2 1 1 ð...

Page 654: ...ated Refer to Extended Line Communication Status ELCS For LCS X D2 for details D4 A scanner internal trace is already running on this interface D6 EAC does not find an end of packet flag in the current internal EAC buffer and does not own the next buffer D8 An unexpected CSP level 2 interrupt from the EAC has occurred DA Indicates that the EAC transmitter has truncated a message due to data late f...

Page 655: ...d g 08 3 DMA time out on write 0A 1 DMA interconnection error in write 10 c SCTL DMA storage protect address exception 12 b SCTL DMA logical error 14 f DMSW main bus parity check 16 Combination of f and h 18 4 DMA time out on read 1A 2 DMA interconnection error on read 22 d Storage unrecoverable error SCTL internal error 24 Combination of e and f 28 g DMSW parity check on primary secondary bus 2A ...

Page 656: ...interrupt request is raised to the CCU The command on the other interface is cleared without any ending status nor level 2 interrupt request to the CCU After such an error the only commands that will be accepted on the line are set mode or enable Residual Count This byte indicates the number of unused bytes remaining in the last buffer used Last Buffer Pointer This three byte address points to the...

Page 657: ...rd When an error is detected in the EAC adapter The microcode issues one single request to the EAC to manage the receive line interface and the transmit line interface Chapter 12 Ethernet Subsystem ESS 12 35 ...

Page 658: ...O operations on the IOC bus These errors may be detected by the CCU or by the ELA Errors are related to CCU storage and address checks invalid sequences and timed out IOH IOHI instructions 2 ELA problems Invalid interrupts Microcode detected program failures These set the microcode check bit in the error status and cause the NCP to issue a get microcode check instruction CCU level 2 interrupt stac...

Page 659: ...r read DMA time out during write or read DMA bus driver fault DMA burst count error DMA interconnection errors for improper DMA tag sequence 3 Errors detected in the SCTL switch cards Storage internal error SCTL internal error DMA internal error DMA logical error DMA storage protect address exception DMA interconnection error in read or write a DMSW parity check main bus b DMSW parity check primar...

Page 660: ...roperly DMA Data Bus Parity Checker This parity checker verifies the validity of the data received sent from to the DMA data bus byte 0 and byte 1 by the EAC DMA Time out One hardware timer is implemented to detect possible time out conditions on the DMA bus The duration of the timer is in the range of 100 ms to cover a complete transfer operation on the DMA bus DMA Burst Count Checker This checke...

Page 661: ...ditions Hexadecimal Code a b c d e f g h i ð Normal mode no error 1 x 2 x 3 x 4 x 5 x 6 x 7 x 8 x 9 x A x x B x x C x x D E F x x x Figure 12 6 Line Error Hexadecimal Code SCTL error detection a DMA internal error b DMA logical error c DMA storage protect address exception error d Storage unrecoverable error or control error e DMA interconnection error Switch card error detection f DMSW parity che...

Page 662: ...corresponding error condition in an error register X 10 and CSP storage Interrupts the CSP microcode 2 The CSP microcode Stops the transmit and receive operations in process In case of transmit puts the transmit data line at mark In case of receive stops the receive command DMA SCTL Errors They are reported by the EAC through a level 2 interrupt and then both interfaces are disabled by the microco...

Page 663: ...ernal register X 03 bit 6 1 and termi nates the operation The EAC does not report any error condition Parity errors occurring on the cycle steal interconnection can be detected by the EAC or by the CSP If the EAC detects a parity error on the data bus during a cycle steal write the EAC sets a level 2 interrupt to the CSP with the CSP interconnection error status set after completing the operation ...

Page 664: ...nterrupt Type 2 Error detected by the CCU during AIO A halt is send to the CSP which results in a CCU or MOSS level 1 interrupt Type 3 Internal logical errors detected by the CSP microcode A CCU level 1 or MOSS level 4 interrupt is set Hard Stop A CSP microprocessor check has been encountered The CSP hard ware responds with the error status The following tables show the detailed responses that may...

Page 665: ...ddress bit 2 x Not used Line interface address bit 3 x Invalid input Line interface IOH address bit 4 x Adapter interconn check Note Next comes the decoding of bits 0 to 7 when command reject occurs Bit Normal Command Trace Command Invalid Output IOH ð123 4567 Reject Reject x Command reject Command reject Always OFF x Always OFF Always ON Invalid output IOH x Not used Not used x Line interface Not...

Page 666: ...k check x Internal check Byte 1 Bit ð 1 2 3 4 5 6 7 Meaning x Unexpected adapter acknowledgment x Control store write data check x Processor check x External register address check x Control store address check x LSR address check Not used Diagnostic Facilities Refer to the 3745 Diagnostic Descriptions SY33 2059 for more details 12 44 IBM 3745 Models 130 150 160 170 and 17A Hardware Maintenance Re...

Page 667: ... storage and registers CSP and EAC Programming Support for Problem Determination It includes as for LSS microcode 1 Error detection 2 Error collection 3 Error reporting Types of errors tracked are CSP IOC bus interconnection errors CSP internal errors CSP EAC interconnection errors DMA SCTL Switch errors EAC errors EAC to line interface errors NCP Buffer Prefix Validity Checking in Receive This te...

Page 668: ...Problem Determination Aid 12 46 IBM 3745 Models 130 150 160 170 and 17A Hardware Maintenance Reference ...

Page 669: ...OSS power ON reset register CARST CA reset register CBC controller bus coupler CBTRA controller bus and token ring adapter CBSA controller bus and service adapter CBSP CBC TIC3 CBSP controller bus and service processor CBx FRU name of circuit breaker number x CCITT Comite Consultatif International Telegraphique et Telephonique CCU central control unit CCW channel command word CD carrier detector s...

Page 670: ...Connection coupler ESCC2 ESCC type 2 ESCP Enterprise system connection processor ESS Ethernet subsystem ETG Ethernet tail gate FAN1 FRU name of the power supply box fan FAN2 FRU name of the logic box fan FCC Federal Communications Commission FDD FRU name of the flexible disk drive FE field engineering FESH FRU name of the front end scanner high speed FRU field replaceable unit ft foot GPT generali...

Page 671: ...s MCAD MOSS CA Adapter MCC FRU name of the MOSS control card MCCU MOSS CCU Adapter MCF microcode fix MCRA mode control register A MCT machine configuration table MDOR MOSS data operand register MES miscellaneous equipment specification MHz megahertz min minute MIO MOSS input output MIOC MOSS I O control bus MIP Maintenance Information Procedures MLA MOSS LAN adapter mm millimeter MMIO memory mappe...

Page 672: ...ture SNRM set normal response mode SDLC SPDn signal and power distribution card SPS service and power support SRC system reference code STAT0 status 0 register STAT1 status 1 register STAT4 status 4 register STO FRU name of the storage card STO4 FRU name of the storage card 4 Mbytes STO8 FRU name of the storage card 8 Mbytes SVC supervisor call SWx FRU name of switch number x T transmit signal TA ...

Page 673: ...thod V 24 CCITT V 24 recommendation V 25 CCITT V 25 recommendation V 28 CCITT V 28 recommendation V 35 CCITT V 35 recommendation WLOB wire lobe cable connecting token ring adapters to token ring access units XI X 25 SNA interconnection XID exchange identification X 21 CCITT X 21 recommendation X 25 CCITT X 25 recommendation List of Abbreviations X 5 ...

Page 674: ...X 6 IBM 3745 Models 130 150 160 170 and 17A Hardware Maintenance Reference ...

Page 675: ...f data transmission where the data passes through the DCE and network and arrives at the receiving communication controller unchanged from the data transmitted The DCE or network can modify the data during transmission because of certain network restrictions but must ensure the received data stream is the same as the transmitted data stream communication controller A communication control unit tha...

Page 676: ...nsed program that provides communication controller support for single domain multiple domain and interconnected network capability operator console The IBM Operator Console that is used to operate and service the communication con troller CC through the MOSS Optionally an alternate console may be installed up to 120 m from the CC or a remote console may be connected to the CC through the switched...

Page 677: ... for this EC SA33 0142 IBM 3745 Communication Controller Models 130 150 160 170 and 17A IBM 3746 Expansion Unit Model 900 Customer Master Indexñ Provides references for finding information in the customer documentation library Evaluating and Configuring GA33 0138 IBM 3745 Communication Controller Models 130 150 and 170 Introduction Gives an introduction about the IBM Models 130 to 170 capabilities...

Page 678: ...uide SA33 0129 Preparing for Operation GA33 0400 IBM 3745 Communication Controller All Modelsó IBM 3746 Nways Multiprotocol Controller Models 900 and 950 Safety Informationñ Provides general safety guidelines SA33 0129 IBM 3745 Communication Controller All Modelsó IBM 3746 Nways Multiprotocol Controller Model 900 Connection and Integration Guideñ Contains information for connecting hardware and in...

Page 679: ... instruction for advanced operations and testing using the 3745 MOSS console On line Information Controller Configuration and Management Application Provides a graphical user interface for configuring and managing a 3746 APPN HPR Network Node and IP Router and its resources Is also available as a stand alone application using an OS 2 workstation Defines and explains all the 3746 Network Node and I...

Page 680: ...el 950 Alert Reference Guide Provides information about events or errors reported by alerts for IBM 3745 Communication Controller Models Aò IBM 3746 Nways Multiprotocol Controller Models 900 and 950 ñ Documentation shipped with the 3745 ò 3745 Models 17A to 61A ó 3745 Models 130 to 61A ô Except 3745 Models A õ Documentation shipped with the 3746 900 X 12 IBM 3745 Models 130 150 160 170 and 17A Har...

Page 681: ...up documentation SY33 2067 IBM 3745 Communication Controller Models 130 150 160 170 and 17A Installation Guideñ Provides instructions for installing or relocating the IBM 3745 Models 1X0 and 17A SY33 2114 IBM 3746 Nways Multiprotocol Controller Model 900 Installation Guideò Provides instructions for installing or relocating the IBM 3746 Model 900 SY33 2116 IBM 3746 Nways Multiprotocol Controller M...

Page 682: ...18 IBM 3746 Nways Multiprotocol Controller Models 900 and 950 Multiaccess Enclosure Installation and Maintenanceô Provides information on installing and maintaining the Multiaccess Enclosure MAE SY33 2112 IBM 3746 Nways Multiprotocol Controller Models 900 and 950 Network Node Processor Installation and Maintenanceô Based on the 7585 or 3172 Provides information on installing and maintaining the ne...

Page 683: ...rmation for ordering parts for the IBM 3746 Models 900 and 950 S135 2012 3745 Communication Controller Models 130 to 17A Parts Catalogñ Provides reference information for ordering IBM 3745 Models 1X0 and 17A parts S135 2014 IBM Controller Expansion Parts Catalog Provides reference information for ordering parts for the controller expansion attached to the IBM 3746 Model 900 and 950 Bibliography X ...

Page 684: ... IBM Networking Softcopy Collection Kit Allows service manuals consulting via CD ROM viewer US version ñ Documentation shipped with the 3745 ò Documentation shipped with the 3746 900 ó 3745 Models 17A to 61A ô Documentation shipped with the processor õ Product integrated information ö 3745 Models 130 to 61A Documentation shipped with the 3746 Models 900 and 950 X 16 IBM 3745 Models 130 150 160 170...

Page 685: ...connection 3 6 address DCE LIC type 6 4 86 address exception CCU 2 18 instruction fetch error CCU 2 47 program execution error CCU 2 47 address register LIC types 1 to 4 4 47 LIC types 5 6 DTE function 4 55 address command tag 3 7 addressing 3746 900 adapter CBC PRC 3 36 CA 3 32 ESS line 3 45 HPTSS line 3 45 LIC board 3 38 LIC1 LIC3 LIC4A and LIC4B 3 40 LIC5 and LIC6 3 42 line 3 39 line adapter LS...

Page 686: ...chanism 11 12 BER continued storage on disk 11 7 structure 11 10 type 11 9 BER analysis 11 18 automatic analysis 11 18 automatic FRU correlation 11 20 CE field updating 11 19 correlation range 11 20 manual analysis 11 19 manual FRU correlation 11 20 BER format on disk 11 112 BER reference code 11 19 11 21 BER type 01 11 33 11 39 summary 11 33 BER type 01 ID 00 detailed BER display 11 39 error code...

Page 687: ...ed BER display 11 184 field description 11 187 formats 11 189 summary 11 179 BER type 12 field description 11 192 formats 11 193 summary 11 191 BER type 13 detailed BER display 11 195 field description 11 196 formats 11 197 summary 11 194 BER type 14 detailed BER display 11 199 field description 11 199 format 11 200 summary 11 198 BER type 15 detailed BER display 11 203 field description 11 206 fo...

Page 688: ...rrors 2 39 in 3745 data flow 2 2 registers 2 21 CCU continued storage interconnection 2 17 storage line invalidation 2 18 storage read policy CCU 2 18 storage write policy 2 18 subsystem POR 2 13 timers 2 19 to and from adapters 2 20 to and from MOSS 2 43 CCU BER See BER type 13 CCU BER formats 11 197 CCU bus 3 4 3 6 function 3 6 CCU to MOSS communication 8 14 CCU adapters interconnection 3 6 CCUI...

Page 689: ...sole attachment alternate 1 17 local 1 17 remote 1 17 RSF 1 17 console sharing via IBM 7427 9 7 consoles tail gate 9 7 contact sense operate from PKD 4 78 contingent allegiance 7 18 control panel 9 2 9 3 connection 9 5 operation 9 5 overview 9 2 reference card 9 4 control program See also NCP generation 1 23 loading 1 23 loading from disk automatic 1 23 multiple load module 1 23 control register L...

Page 690: ... 5 11 data streaming 7 5 data tag 3 7 data transfer methods 7 9 data transfer state CA 7 10 data transmission HSS 5 10 data value register CCU 2 43 DC voltage test points PS1 10 9 DC voltages and tolerances CSP FESH EAC cards 10 12 disk 10 14 diskette 10 14 PS1 10 10 PS2 10 13 DCE address LIC type 5 4 69 address LIC type 6 4 86 information on PKD 4 75 DCE clock failure FESH 5 20 DCE to telephone l...

Page 691: ...r layer 12 16 errors reporting 5 26 12 40 HSS DMA manager layer 5 14 interconnection errors detected by EAC 12 38 interconnection errors detected by FESH 5 24 logic CCU 2 15 operation TRA 6 17 DMA continued size 5 22 tag sequence 5 24 12 38 time out 5 25 12 38 DMA interconnection errors detected by EAC 12 38 DMA to SCTL bus line function 3 11 DMUX double multiplexer card definition 4 8 functional ...

Page 692: ...ess exception instruction fetch error CCU 2 47 address exception program execution error CCU 2 47 CCU detected hardware errors 2 44 CCU detected not hard errors 2 44 CCU hard errors 2 39 control ROS parity error CCU 2 46 D1 D2 register parity errors two errors CCU 2 46 detected by TRM format 1 6 22 detection CCU 2 46 detection and reporting ELA 12 36 HSS 5 23 TRM 6 20 DMA bus errors reported by FE...

Page 693: ...4 7 CSP interconnection 4 28 data flow 4 27 data RAM 4 31 definition 4 27 description 4 28 external register X 13 4 29 external register X 15 4 29 inbound and outbound control RAM 4 29 inbound outbound RAM addressing 4 29 inbound outbound RAM layout 4 29 local store 6 4 29 RAM organization 4 28 serial link interconnection 4 28 FESH card 5 12 CTS state confirmation 5 20 DCE clock failure 5 20 DCE i...

Page 694: ...ted by CSP hardware HSS 5 30 hard stop error status detected by CSP hardware 12 44 hard stop transmit command HSS 5 17 hardstop CSP 4 18 hardware error detection and reporting ELA 12 36 hardware error status for ESS 12 34 hardware error status initial status B 111 5 36 hardware error status initial status B 111 for ESS 12 34 hardware error status initial status B 111 for HSS 5 36 hardware errors C...

Page 695: ...9 initial status B 110 internal box error ESS 12 32 initial status B 110 internal box error HSS 5 34 initial status field ISF bit definition 5 32 initial status field bit definition for ESS 12 30 initialized 4 19 inoperative 4 19 input and output X 7x register bits CCU 2 28 input instructions details CCU 2 25 input instructions CCU 2 23 input output 3 7 input output instruction formats ELA 12 25 i...

Page 696: ...47 IOC bus interconnection TRA 6 16 bus to CSP interconnection ELA 12 13 bus to CSP interconnection HSS 5 10 control logic CCU 2 20 data flow CCU 2 20 IOC BER See BER type 14 IOC BER format 11 200 IOC bus 3 4 physical interconnection 3 9 protocol 3 4 scoping routine 3 53 adapter selection 3 54 ERC meaning 3 56 error bit 3 56 examples 3 58 how to start 3 53 parameter description 3 54 RAC meaning 3 ...

Page 697: ... 69 host support 4 70 line quality threshold 4 69 line specifications 4 65 LIC type 5 DCE function continued line spectrum 4 65 LPDA 2 hit count threshold 4 69 LPDA 2 enabled 4 70 maintenance approach 4 57 manual tests 4 72 microcode EC level 4 70 multipoint LIC type 5 to 586Xs 4 59 multipoint LIC type 5 to LICs type 5 4 59 multipoint LIC type 5 to one tailed 586X 4 60 native mode 4 62 4 63 option...

Page 698: ... 11 transfer mode 4 11 LIC types 5 6 continued transmission speed 4 11 LIC types 5 6 DTE function address register 4 55 control register 4 55 LIC reset 4 54 line enable disable 4 55 loop 3 on V 24 4 56 selective scanning 4 55 swap 4 55 transmit receive mechanism 4 54 wraps 4 55 LIC1 LIC3 LIC4A and LIC4B addressing 3 40 LIC5 and LIC6 addressing 3 42 limited distance LIC type 6 connection 4 80 line ...

Page 699: ...k LIC 5 6 4 96 loop 3 LIC type 6 4 87 local loop back LIC 5 6 4 96 loop 3 continued on V 24 LIC types 1 to 4 4 52 on V 24 LIC types 5 6 DTE function 4 56 on X 21 LIC types 1 to 4 4 52 loop back local LIC type 6 4 89 loop or wrap tests for HSS V 35 and X 21 5 39 loosely coupled 7 17 low speed scanner 1 9 See also LSS low speed scanner LPDA 2 enabled LIC type 5 4 70 hit count threshold LIC type 5 4 ...

Page 700: ...so BER type 01 MOSS BER formats 11 112 MOSS board DC voltages and tolerances 10 10 MOSS check 11 30 MOSS check codes 11 40 MOSS ID 06 formats 11 33 MOSS to CCU communication 8 14 MOSS disk diskette drive interaction 8 19 MOSS operator console connections 8 20 MSAU TRSS 6 6 multi floor wiring example 6 9 multipoint LIC type 5 DCE function 4 69 LIC type 5 to 586Xs connection 4 59 LIC type 5 to LICs ...

Page 701: ...ion LIC type 4 4 48 physical address wiring 3 31 physical interconnection DMA bus 3 10 IOC bus 3 9 physical link status definition 11 208 pin assignment bus terminator 3 60 ping pong buffers 4 18 clocks 4 18 PIO operation sequence 3 15 data transfer 3 17 initialization 3 16 read halfword adapter 3 18 write halfword adapter 3 18 PKD portable keypad display analog test 4 77 background information 4 ...

Page 702: ...r LIC types 1 to 4 4 92 aid for LIC types 5 6 4 95 problem determination continued aid on HSS 5 37 aid on TRA 6 27 aids ELA 12 45 CCITT loop 3 4 87 commands LIC type 5 DCE function 4 70 commands LIC type 6 4 86 programming support ELA 12 45 programming support HSS 5 37 self test 4 87 problem isolation and network management HSS 5 38 processor unit CCU 2 4 program display register 1 CCU 2 43 progra...

Page 703: ... 2 42 registers CA 7 10 REM DSU CSU FAILED 4 90 REM MODEM FAILED 4 79 REM PWR LOSS 4 79 4 90 remote self test 4 97 status 4 98 remote console 9 6 Remote Support Facilities RSF 8 20 remote support facility 1 17 9 7 removing CA from CS chain 7 14 reporting DMA errors 5 26 12 40 request unit 8 16 reset 3 9 AIO CCU 2 21 CSP 4 20 DMUX 4 37 EAC 12 17 FESH 5 15 FESL 4 25 LIC 4 38 4 42 LIC types 1 to 4 4 ...

Page 704: ...rsonnel definitions xiii service processor 9 8 SES bit definition 5 31 set and reset the bypass CCU check stop mode 2 44 set and reset the level 1 adapter mask CCU 2 44 set line vector table high ELA 12 27 low ELA 12 27 set special line vector table high ELA 12 28 low ELA 12 28 setting interrupt requests CCU 2 7 setup of the console 9 8 short hold mode multiple port sharing 1 22 signals used by CA...

Page 705: ...stem components TRSS 6 7 system environment ELA 12 5 system environment HSS 5 5 system reset on CA 7 19 system support programs 1 20 T tag reset TRA 6 19 tag sequence DMA 5 24 12 38 tagged DE status 7 18 tail gate for consoles 9 7 TD fields ELA 12 26 test analog line analysis 4 99 digital xmit rcve LIC type 5 4 98 digital xmit rcve LIC type 6 4 99 manual from PKD LIC types 5 6 4 95 manual LIC type...

Page 706: ...4 40 transmit receive LIC types 1 to 4 4 44 TRM token ring multiplexor arbitration mechanism 6 18 card 6 15 error detected by TRM format 1 6 22 TRM token ring multiplexor continued error status register level 1 6 20 register level 2 6 22 TRSS 1 14 cabling system 6 5 cpckaging TRSS 6 10 major system components 6 7 nodes 6 8 ring 6 5 ring access protocol 6 7 TRSS BER See BER type 15 TRSS BER formats...

Page 707: ...5 LIC types 1 to 4 4 93 LIC types 5 6 4 95 controlled from MOSS 4 94 4 95 LIC types 1 to 4 4 94 LIC types 5 6 4 95 WRONG SLOT 4 79 4 90 X X 13 register FESA line interface address 4 29 X 15 register FESA asynchronous operation command 4 29 X 75 register LA CA addresses decoding 2 33 X 21 clear 4 33 example of two cables connected HSS 5 41 interface HSS 5 41 loop 1 LIC types 1 to 4 4 52 loop 3 LIC ...

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Page 709: ...ur comments concerning this book We will greatly appreciate them and will consider them for later releases of the present book If you prefer sending comments by FAX or electronically use FAX 33 4 93 24 77 97 E mail FRIBMQF5 at IBMMAIL IBM Internal Use LGERCF at LGEPROFS Internet rcf_lagaude vnet ibm com In advance thank you Your comments Name Address Company or Organization Phone No ...

Page 710: ...ts We d Like to Hear from You SY33 2066 4 IBM Fold and Tape Please do not staple Fold and Tape PLACE POSTAGE STAMP HERE IBM France Centre d Etudes et Recherches Service 0798 BP 79 06610 La Gaude France Fold and Tape Please do not staple Fold and Tape SY33 2066 4 ...

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Page 712: ...IBM Part Number 03F5010 Printed in Denmark by IBM Danmark A S ð3F5ð1ð SY33 2ð66 4 ...

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