MOSS Error Status Register
Format 1 is used for errors detected by TRM in MOSS PIO/MMIO operations or in direct memory access
(DMA) operations (TIC to CCU storage).
TD Field Byte ð
(Byte 1 not Used)
ð
1
2
3
4
5
6
7
┌───────┬───────┬───────┬───────┬───────┬───────┬───────┬───────┐
│
1
│
Error Encoding
│
Error Encoding
│
ð
│
└───────┴───────┴───────┴───────┴───────┴───────┴───────┴───────┘
└──────────┬──────────┘ └──────────┬──────────┘
6
6
TRM error found in MIOH
Error found in DMA for TIC
under MOSS control
Error encoding:
0 0 0
No error
0 0 1
TRM internal
0 1 0
TIC interconnection type 1
0 1 1
TIC interconnection type 2
Internal
The TRM is suspected.
Type 1
The working TIC is suspected.
Type 2
All TICs are suspected.
The MOSS error status register is used to log errors associated with MOSS operations. If a MOSS control
bit in the TIC control register is ON, all MMIO and DMA errors for that TIC will be logged in the MOSS
error status register.
If the TRM is connected, all MIOH/MMIO errors will be logged in the MOSS error status register.
If the TRM is disconnected and the associated MOSS control bit is OFF, all MMIO and DMA errors for a
TIC are logged in the normal level 2 error status register.
Format 2 is not used for the MOSS error status register.
TIC Adapter Check Register
The adapter check interrupt is generated when the TIC has encountered an unrecoverable hardware or
microcode error. In this case the TIC is waiting for a reset.
The reason for the TIC check is located in 8 bytes beginning at address X'05E0'. The TIC check status is
defined as follows:
X'5Eð' (TIC adapter storage)
┌───────────────┬───────────────┬───────────────┬───────────────┐
│ Byte ð and 1
│ Byte 2 and 3
│ Byte 4 and 5
│ Byte 6 and 7
│
├───────┬───────┼───────┬───────┼───────┬───────┼───────┬───────┤
│ Adapter check │
Parameter ð
│
Parameter 1
│
Parameter 2
│
└───────┴───────┴───────┴───────┴───────┴───────┴───────┴───────┘
Each bit of the TIC adapter check gives the error type and the contents of parameters 0 to 2 give addi-
tional information. More details are given in the following table.
6-24
IBM 3745 Models 130, 150, 160, 170, and 17A: Hardware Maintenance Reference
Summary of Contents for 3745 Series
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Page 21: ...3745 Models 130 150 160 and 170 Data Flow Chapter 1 General Information 1 3 ...
Page 149: ...For RACs 241 to 244 ERR bits Data received from the adapter Chapter 3 Buses 3 57 ...
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Page 169: ...Chapter 4 Transmission Subsystem TSS 4 17 ...
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Page 625: ...The ESS in 3745 Models 130 150 160 and 170 Data Flow Chapter 12 Ethernet Subsystem ESS 12 3 ...
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