IBM 3745 Series, Hardware Maintenance Reference

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Summary of the IOC Bus Interface Signal Lines
┌──────────────────────┬──────────┬───────────┬───────┬───────┬───────┐
│
Signal Line Names │ Mnemonic │ Initiated │ PIO/ │ AIO │ Inter-│
│ │ │ by │ TRM │ │ rupt │
├──────────────────────┼──────────┼───────────┼───────┼───────┼───────┤
│ Card present IN
│ + PREIN │ Adp.before│ X │ X │ │
│ Card present OUT │ + PREOUT │ TRM │ X │ X │ │
│ Cycle steal request │ + CSRH │ TRM │ │ X │ │
│ high │ │ │ │ │ │
│ Cycle steal grant │ + CSGH │ CCU │ │ X │ │
│ high │ │ │ │ │ │
│ Cycle steal grant │ + CSGHP │ CCU │ │ X │ │
│ high previous │ │ │ │ │ │
│ Cycle steal priority │ + CSPRY │ TRM/adapt.│ │ X │ │
│ line │ │ │ │ │ │
│ CSG through tag │ + CSGT │ TRM │ │ X │ │
│ IOC data bus │+DO - +D15│ TRM/CCU │ X │ X │ X │
│ End of chain │ + EOC │ TRM │ │ X │ │
│ Halt │ + HALT │ CCU │ X │ X │ │
│ Input/output │ + I/O │ CCU │ X │ X │ │
│ Interrupt request │ + IRR │ TRM │ X │ X │ │
│ removed │ │ │ │ │ │
│ Interrupt to MOSS │ +ITMOSS │ TRM │ X │ X │ X │
│ Level 2 priority line│ +L2PRY │ TRM/adapt.│ │ │ X │
│ Level 2 serial select│ +L2SSLIN │ Adp.before│ │ │ X │
│ line in │ │ │ │ │ │
│ Level 2 serial select│ +L2SSINP │ Adp.prev. │ │ │ X │
│ line in previous │ │ │ │ │ │
│ Level 2 serial select│ +L2SSLOU │ Adp.prev. │ │ │ X │
│ line out │ │ │ │ │ │
│ Modifier │ + M │ TRM │ │ X │ │
│ Parity valid │ + PV │ TRM │ X │ X │ │
│ Parities │ +Pð,+P1 │ TRM/CCU │ X │ X │ X │
│ Power on reset │ ─ POR │ Power blck│ │ │ │
│ Reset │ + RESET │ Switch │ │ │ │
│ TA │ + TA │ CCU │ X │ │ │
│ TD │ + TD │ CCU │ X │ X │ │
│ Valid halfword │ + VH │ TRM │ X │ X │ X │
│ Valid byte │ + VB │ TRM │ │ X │ │
└──────────────────────┴──────────┴───────────┴───────┴───────┴───────┘
Figure 6-14. Summary of the IOC Bus Interconnection Signal Lines
TIC Bus Interconnection
The TIC bus is a bidirectional bus which connects the TRM card to the TIC cards via the card bottom
connector I/O pins and the board.
Three types of operation are used on this interface:
Ÿ Direct memory access (DMA)
Ÿ Memory mapped input/output (MMIO)
Ÿ
Interrupt acknowledgement (IACK).
DMA Operation
The DMA operation allows transferring a burst of data between the TRM and the
TIC.
:
During DMA operations, the TIC controls the bus and the TRM is the tributary unit.
MMIO Operation
The MMIO allows access to the registers of the IOC interconnection control of the
TIC.
Chapter 6. The Token-Ring Subsystem
6-17