IBM 3745 Series, Hardware Maintenance Reference

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Output X'7A' (utilization counter):
This instruction causes the contents of the specified general register to control
the high-resolution timer and the utilization counter.
Output X'7B' (set PCI level 2):
This instruction causes a program-controlled interrupt request to be set for
program level 2 (PCI level 2). This allows a program level to transfer a proc-
essing requirement to a different priority program level. The bit settings of the
general register are ignored. A PCI interrupt request is immediately effective.
Output X'7C' (set PCI level 3):
This instruction causes a program-controlled interrupt request to be set for
program level 3 (PCI level 3). This allows a program level to transfer a proc-
essing requirement to a different priority program level. The bit settings of the
general register are ignored. A PCI interrupt request is immediately effective.
Output X'7D' (set PCI level 4):
This instruction causes a program-controlled interrupt request to be set for
program level 4 (PCI level 4). This allows a program level to transfer a proc-
essing requirement to a lower priority level. The bit settings of the general reg-
ister are ignored. A PCI interrupt request is immediately effective.
Output X'7E' (set mask bits):
This instruction causes the mask bits of the program levels to be set according
to the contents of the general register. When a mask bit is set ON, interrupt
requests for the program level that corresponds to that bit are ignored. When
the mask bit for program level 5 is ON, program execution at that level is not
allowed.
Output X'7F' (reset mask bits):
This instruction causes the mask bits of the program levels to be reset
according to the contents of the general register. If an interrupt for a particular
level is pending when the mask bit for that level is reset, an interrupt for that
level will occur before the next instruction is executed.
Chapter 2. Central Control Unit (CCU)
2-27