Function Partitioning
The SCTL card can be partitioned into three distinct functional parts:
The central control unit interconnection (CCUI) logic
The direct memory access (DMA) logic
The storage control (MCTL) and, error checking and correction (ECC) logic.
S C T L
──┐
┌─────────────────────────┬───────────────┐
C │
│
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C C U I
L o g i c
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H │%─────────5│
M C T L
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B │
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and
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──┘
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├─ ── ── ── ── ── ── ── ──┤
E C C
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└──
──┘
└─────────────────────────┴───────────────┘
CCUI logic
The CCUI logic interconnects the CCU cache storage. It receives and buffers
requests from CCU/cache and controls cache line loading. It controls cache
line invalidation and accesses the DMA storage protect RAM (during DMA write
operations) on behalf of the DMA logic. The CCUI logic makes storage
requests to the MCTL/ECC.
DMA Logic
The DMA logic interconnects the DMA bus on which the high-speed adapters
are hooked. It receives requests from the high-speed adapters. It performs
data alignment, reads or writes its DMA buffer and makes storage requests to
the MCTL and ECC. During a DMA write storage transfer, it makes requests to
the CCUI logic for cache line invalidations and for access to the DMA storage
protect RAM.
MCTL and ECC
The MCTL and ECC interconnects the storage. It receives storage requests
from the CCUI logic and the DMA logic. It performs arbitration between these
two users, accesses storage and controls the ECC mechanism.
The storage control contains an error correction code (one word) which is per-
manently stored, either with its original parity or inverted, thus allowing to
correct at least one error in addition to the one-bit correction.
The correcting capability of the ECC depends on the type of bit error, whether it
is a hard error (storage position stuck to 0 or 1), or a soft (transient) error.
Chapter 2. Central Control Unit (CCU)
2-15
Summary of Contents for 3745 Series
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