IBM 3745 Series, Hardware Maintenance Reference

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Unresolved Interrupts
The control program logs BERs based on 'unresolved situations' (see
"BER/Alarm/Alert/Mechanisms" page 11-12).
Unresolved Level 1 CA Adapter Error (BER 10 ID 9E)
There are two possible types of unresolved CA level 1 interrupts.
Ÿ A CA level 1 occurs and no bit is ON in the CA external register X'E'.
Ÿ There is a CA level 1 and none of the following bits is ON in the CA external
register X'D':
– 0.0 IOC bus parity error
– 0.1 internal bus parity error
– 0.2 CCIN card check
– 0.4 CHIN card check
– 0.5 address compare error
– 1.0 output exception check
– 1.1 PIO halt remember latch
– 1.2 cycle steal halt remember latch
– 1.3 bus in check interface A
– 1.6 CADR card check interface A
The following bits are checked in X'0'. If none is ON, the control program builds a
BER 10 B1:
Ÿ
0.0 (normal) initial selection interrupt
Ÿ 0.1 interface disconnect
Ÿ 0.2 selective reset
Ÿ 0.3 channel bus out check
Ÿ
0.5 stacked initial status
Ÿ
0.6 ESC status byte cleared
Ÿ 0.7 system reset.
Unresolved Level 3 CA Data/Status (BER 10 ID B2)
The following bits in are checked in X'2'. If none of these bits is set and the system
reset bit in X'0' is not set ( bit 0.7), the control program builds a BER 10 B2:
Ÿ 0.0 outbound data transfer sequence
Ÿ 0.1 inbound data transfer sequence
Ÿ 0.2 (final) status transfer sequence
Ÿ 0.5 channel stop/interface disconnect
Ÿ
0.6 suppress out monitor interrupt
Ÿ
1.1 data/status selective reset
Ÿ 1.3 stacked ending status.
Chapter 11. Error Logging
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