IBM 3745 Series, Hardware Maintenance Reference

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Reset (RST): The MOSS may activate the 'reset' line at any time to initialize all
adapters. This initialization will cause all adapters to immediately terminate current
operations, go to a ready state, and prepare to respond to PIO commands.
Data bus bytes 0 and 1: The data bus is halfword wide with 18 bidirectional lines.
Each of the two bytes (0 and 1) contains 8 bits plus a parity bit (0-7,P).
Information is transferred between the CCU and the adapters in either direction
when the 'I/O' line is active.
Four bits of the bus are used for an additional function when the 'I/O' line is deacti-
vated, as follows:
Ÿ
Byte 0 bit 1 = LAs Level 2 interrupt request to CCU.
Ÿ Byte 0 bit 5 = CAs Level 1 interrupt request to CCU.
Ÿ Byte 1 bit 0 = CAs Level 3 interrupt request to CCU.
Ÿ Byte 1 bit 5 = LAs Level 1 interrupt request to CCU.
The adapters activate their interrupt requests to the CCU using these paths, but
only when the 'I/O' line is inactive.
The CCU will sample the data bus for interrupts after activating the 'TD' line, while
the 'I/O' line is inactive.
Scanner Interrupt (Scan Int): Interrupt level 4 generated by the line adapter to
the MOSS (MPC).
Physical Interconnection
The physical interconnection is made by board wiring.
See Figure 3-2 on page 3-5.
Chapter 3. Buses
3-9