IBM 3745 Series, Hardware Maintenance Reference

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Bit 6 This bit (TD) is ON if the TD tag into the TRM is active when the halt tag is activated.
Bit 7 This bit (disconnect) is ON if the TRM is in disconnect mode when the read level 1 error status
register PIO is executed.
Bit 8 This bit (TA select) is ON if the TRM has recognized its address (with good parity) and the PIO
has not completed when the halt tag is activated.
Bit 9 This bit (CS select) is ON if the TRM has trapped CSG for an AIO and the AIO has not com-
pleted when the halt tag is activated.
Bit 10 This bit (TIC bus idle) is ON if the TRM detects that the TIC bus is idle when the halt tag is
activated.
Bit 11 This bit (CCU PIO disable) is ON if the TRM is disabled for CCU PIOs when the read level 1
error status register is executed.
If the TRM is CCU PIO disabled, the level 1 error status register can be successfully read only
by an MIOH.
Bit 12 This bit (TRM/TIC) is ON if an AIO or a get line ID PIO is being executed by the TRM when the
halt tag is activated.
If this bit is ON, it means that bits 13 and 14 are valid.
If this bit is OFF, it means that the error cannot be associated with any particular TIC.
Bits 13 and 14 Bits 13 and 14 are used to encode the TIC number for some errors.
During a cycle steal operation, bits 13 and 14 are used to identify the TIC that was doing the
DMA operation when the halt tag was received. They also indicate the originator of the level 2
interrupt for an error during a get line ID PIO. These bits are valid only if bit 12 is ON.
00=TIC 1
01=TIC 2
Bit 15 This bit (invalid IOH) is ON if the TRM decodes an invalid PIO type when the halt tag is acti-
vated. This bit is valid only if bit 5 is ON.
Chapter 6. The Token-Ring Subsystem
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