IBM 3745 Series, Hardware Maintenance Reference

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FESL Reset
The FES (part of the CSC card) can be reset from the CSP by a programmed reset. The FES reset is
sent to the FESA to reset:
Ÿ
The FESA
Ÿ The MUXs
Ÿ The attached LICs.
FESL Reset Flow
CSP microcode
│ │
│ POR Microcode │
│ programmed reset │
│ │ │ │
│ ┌───┬─┴─┐ R'ð4' │ │
│ │ 1 │ 2 ├──%─────────Set/reset──┤ │
│ └───┴─┬─┘ │ │
│ FES│reset │ │
└─CSP───x─────────────────────────x──────────────┘
│ │
┌─FESL──x─────────────────────────x──────────────┐
│
│ FES 6 │
│ 6 ┌───┬───┬───┐ │
│ Reset FES latches │ ð │ 1 │ 2 │ X'17' │
│ │ ┬ └─┬─┴─┬─┴─┬─┘ │
│ Reset FES RAM │ │ │ 6 │
│ │ │ │ 6 FES freeze │
│ FES freeze │ │ Reset FES RAM │
│ │ Reset FES latches │
│ 6 6 │
│ ┌─────────┴───────────┘ │
├─ ── ──│── ── ── ── ── ── ── ── ── ── ── ── ── ─┤
│
│ FESA │
│ Reset tag Control reg. X'A' │
│ │ ┌───┬───┬───┐Addr ðð│
│ 6 │ ð │ 1 │ 2 │ │
│ Reset FESA latches └─┬─┴─┬─┴─┬─┘ │
│ │ ┬ │ │ 6 │
│ Reset FESA RAM │ │ 6 FESA freeze│
│ │ 6 Reset FESA RAM │
│ │ Reset FESA latches │
│ ├──────────┘ │
└───────────────────┼────────────────────────────┘
│ Serial link
6 to MUX
Power ON Reset
The FES 'reset line' signal is driven by CSP R'04' bit 2. This bit is set by the hardware in case of POR, or
by the microcode in case of programmed reset. It is reset by the microcode. This 'FES reset' signal:
1. Resets the FES latches and sets the FESA reset tag.
2. Disables the lines between the CSP and the FES.
3. Resets the FES RAMs: all bits are set to zero and the correct parities are written.
4. Stops all scanning (the FES remains in the freeze state after this reset).
The reset tag from FES starts the following sequence in the FESA:
1. Reset FESA latches and set FESA serial link to 'no transmission'.
2. When reset OFF, reset FESA RAMs.
Chapter 4. Transmission Subsystem (TSS)
4-25