IBM 3745 Series, Hardware Maintenance Reference

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Program level 3
Normal operational interrupt requests from the channel adapters, interval timers and program-
controlled interrupt 3 (PCI) requests and panel interrupts are assigned to this level.
Program level 4
Certain program controlled interrupt (PCI) requests and the supervisor call (SVC) request (generated
when the exit instruction is executed at program level 5), and MOSS request service and request
response are assigned to this interrupt program level. This level is the lowest priority interrupt level.
Program level 5
This level is the lowest priority level and is normally active when none of the other four levels requires
program cycles.
Masking Program Level Priorities:
Programs at levels 1, 2, 3, or 4 can mask all interrupt
requests for program levels 2, 3, or 4 and can mask adapter interrupt requests for level 1. Moreover,
program execution in level 5 can be masked.
The normal operational priority structure can be changed by output instructions X'7E' and X'7F' (set or
reset mask register).
When the mask is set for one or more of program levels 2, 3, or 4, interrupt requests for those levels will
not cause an interrupt. When the mask is set for program level 1, requests by adapters for level 1 will not
cause an interrupt though any other request will be honored.
When the mask for level 5 is set, the use of machine cycles for program execution in level 5 is prevented.
Thus, level 5 program execution is masked. In this case, when no program is executing in levels 1, 2, 3,
or 4, the CCU enters the wait state and no program executes.
To selectively mask one or more program levels, one of the active general registers is loaded with the bits
corresponding to those program levels to be masked. Output instruction X'7E' (set mask register) is then
executed using the general register as input to the mask register. To selectively unmask one or more
program levels, the same procedure is followed except that the output X'7F' (reset mask register) instruc-
tion is executed.
Interrupts
The communication controller operates in response to requests from either the control program (CP) or the
hardware. Since these requests may have varying degrees of urgency, a priority system is used. Each
program, CCU and adapter request, is assigned a particular priority level. A request for use of the con-
troller by the control program or hardware functions is called an interrupt request.
Interrupt Mechanism:
The interrupt mechanism determines when an interrupt can be handled. If
the interrupt request is to be allowed, the change from the active program level to the interrupting program
level takes place immediately after completion of the current instruction. If several interrupt requests
having different priorities are present at the same time, the one with the highest priority obtains use of the
controller. When an interrupt request is granted use of the controller, it can be interrupted in that use by
another request having a higher priority.
When an interrupt occurs, instruction execution at the lower priority program level is suspended until
instruction execution is completed at the higher priority level. An interrupt to a specific program level
prevents future interrupt requests assigned to either that level or to lower priority program level from
causing another interrupt until the servicing of the first interrupt is complete.
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IBM 3745 Models 130, 150, 160, 170, and 17A: Hardware Maintenance Reference