Application Note
AN_289 FT51A Programming Guide
Version 1.0
Document Reference No.: FT_000962 Clearance No.: FTDI# 483
85
Copyright © 2015 Future Technology Devices International Limited
2.10.8.2
Settling Time Examples (for optimal performance)
The ADC function has the following characteristics:
DAC max settling time
0.245µs
Sample & Hold, max settling time
11.8µs
Sample & Hold Settling time
Given the following settings:
System clock frequency
48MHz
Clk_div_sel
0
SH Settling Time Value
0x237 (567)
The divided clock is 48 MHz / (0+1) = 48 MHz, giving a period of 20.83 ns.
Therefore, the allowed Sample & Hold settling time will be 567×20.83 =11.8 us.
For optimal ADC performance, it is recommended that the AIO_SH_COUNTER
default value of 0x139 is overwritten with 0x237, i.e. overwrite the
AIO_SH_COUNTER_L register with the value 0x37 and the AIO_SH_COUNTER_H
register with the value of 0x02.
Assuming a system clock of 48MHz is used and an AIO Clock Division ratio of 0
(default value).
2.10.8.3
AIO_CLOCK_DIVIDER
Bit
Position
Bit Field Name
Type
Reset
Description
7:0
clk_div_sel
R/W
0
This value will be used to select the
division ratio used to divide the
system clock going to the AIO
module. The divided clock frequency
will be:
sys_clk/clk_1
clk_div_sel bits
Clock Divider
000
1
001
2
010
3
011
4
100
5
…
…
111
256
Table 2.111 Clock Divider Register
