FTDI FT51A, Application Note

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Application Note
AN_289 FT51A Programming Guide
Version 1.0
Document Reference No.: FT_000962 Clearance No.: FTDI# 483
36
Product Page
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2.4 SPI Slave
The Serial Peripheral Interface Bus is an industry standard communications interface. Devices
communicate in Master or Slave modes, with the Master initiating the data transfer.
The SPI Slave module has four signals:
- Clock
- Slave Select
- MOSI (master out – slave in)
- MISO (master in – slave out).
The SPI Slave protocol by default does not support any form of handshaking and the only available
mode is unmanaged. Data is clocked out of the Master and clocked in from the Slave
simultaneously.
Figure 2.2 SPI Slave Schematic Diagram
The registers associated with the SPI Slave are outlined in Table 2.36.
I/O
Address
Register Name Description
0x48
SPI_SLAVE_CONTROL
SPI Slave Control Register
0x4A
SPI_SLAVE_DATA_TX
Transmit data register
0x4B
SPI_SLAVE_DATA_RX
Receive data register
0x4C
SPI_SLAVE_IEN
Interrupt Enable register
0x4D
SPI_SLAVE_INT
Interrupt Status register
0x4E
SPI_SLAVE_SETUP
Setup register
Table 2.36 SPI Slave Register Addresses
The SPI Slave module uses a four wire interface: MOSI, MISO, CLK and SS# as shown in Figure
2.2
The main purpose is to send data from main memory to the attached SPI master, and or receive
data and send it to main memory. The SPI Slave is controlled by the internal CPU using internal
memory-mapped I/O registers. It operates from the main system clock, although sampling of
input data and transmission of output data is controlled by the SPI clock (CLK). An SPI transfer
can only be initiated by the SPI Master and begins with the slave select signal being asserted. This
External - SPI Master SPI Slave
CLK
SS#
MISO
MOSI