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FTDI FT51A, Application Note

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FTDI FT51A Application Note Download Page 60

 

Application Note 

 

AN_289 FT51A Programming Guide 

 

Version 1.0 

 
 

Document Reference No.: FT_000962    Clearance No.: FTDI# 483 

 

 
 

59 

Product Page

 

 

Document Feedback

 

Copyright © 2015 Future Technology Devices International Limited 

 

2.8

 

GPIOs 

GPIOs are divided into Digital and Analogue pads. Digital inputs and outputs should be mapped to 
the  digital  pads  but  can  be  mapped  to  analogue  pads  if  required.  Analogue  inputs  and  outputs 
must be mapped to the analogue pads. 

2.8.1

 

Digital GPIO Pads 

Up to 16 digital GPIO pads are available depending on package type. The digital pads are  multi-
speed, multi-voltage and bidirectional I/O. 

The digital GPIO is able to operate over wide voltage ranges and the GPIO voltage can be taken 
above that of the internal supply rails (i.e. up to 5v).  

Each of the 16 digital GPIO pads has its own control register as shown in Table 2.70.  

 

I/O 

Address 

Register Name 

Description 

0x1A 

DIGITAL_CONTROL_GPIO_0

 

Control register for DIO 0 

0x1B 

DIGITAL_CONTROL_GPIO_1

 

Control register for DIO 1 

0x1C 

DIGITAL_CONTROL_GPIO_2

 

Control register for DIO 2 

0x1D 

DIGITAL_CONTROL_GPIO_3

 

Control register for DIO 3 

0x1E 

DIGITAL_CONTROL_GPIO_4

 

Control register for DIO 4 

0x1F 

DIGITAL_CONTROL_GPIO_5

 

Control register for DIO 5 

0x20 

DIGITAL_CONTROL_GPIO_6

 

Control register for DIO 6 

0x21 

DIGITAL_CONTROL_GPIO_7

 

Control register for DIO 7 

0x22 

DIGITAL_CONTROL_GPIO_8

 

Control register for DIO 8 

0x23 

DIGITAL_CONTROL_GPIO_9

 

Control register for DIO 9 

0x24 

DIGITAL_CONTROL_GPIO_10

 

Control register for DIO 10 

0x25 

DIGITAL_CONTROL_GPIO_11

 

Control register for DIO 11 

0x26 

DIGITAL_CONTROL_GPIO_12

 

Control register for DIO 12 

0x27 

DIGITAL_CONTROL_GPIO_13

 

Control register for DIO 13 

0x28 

DIGITAL_CONTROL_GPIO_14

 

Control register for DIO 14 

0x29 

DIGITAL_CONTROL_GPIO_15

 

Control register for DIO 15 

Table 2.70 GPIO DIO Digital Control Register Addresses 

Summary of Contents for FT51A

Page 1: ...Future Technology Devices International Limited FTDI Unit 1 2 Seaward Place Glasgow G41 1HH United Kingdom Tel 44 0 141 429 2777 Fax 44 0 141 429 2758 Web Site http ftdichip com Copyright 2015 Future...

Page 2: ...ns 11 2 2 Device Control Registers 12 2 2 1 DEVICE_CONTROL_REGISTER 13 2 2 2 SYSTEM_CLOCK_DIVIDER 14 2 2 3 TOP_USB_ENABLE 16 2 2 4 PERIPHERAL_INT0 17 2 2 5 PERIPHERAL_IEN0 17 2 2 6 PERIPHERAL_INT1 18...

Page 3: ...2 4 1 SPI_SLAVE_CONTROL 37 2 4 2 SPI_SLAVE_TX_DATA 37 2 4 3 SPI_SLAVE_RX_DATA 38 2 4 4 SPI_SLAVE_IEN 38 2 4 5 SPI_SLAVE_INT 39 2 4 6 SPI_SLAVE_SETUP 40 2 5 I2C Master 41 2 5 1 I2CMSA 41 2 5 2 I2CMCR...

Page 4: ...64 2 9 4 IOMUX_INPUT_SIG_SEL 64 2 9 5 IOMUX_INPUT_PAD_SEL 65 2 9 6 IOMUX Pad Values 65 2 9 7 IOMUX Output Signal Mapping Values 66 2 9 8 IOMUX Input Signal Mapping Values 68 2 9 9 Use Cases 69 2 10 An...

Page 5: ...0 2 12 9 PWM_OUT_CLR_EN 111 2 12 10 PWM_CTRL_BL_CMP8 111 2 12 11 PWM_INIT 111 2 12 12 Use Cases 111 2 13 Timers 115 2 13 1 TIMER_CONTROL 116 2 13 2 TIMER_CONTROL_1 117 2 13 3 TIMER_CONTROL_2 117 2 13...

Page 6: ...2 14 16 DMA_AFULL_TRIGGER_x 135 2 14 17 Use Cases 135 3 Application Guide 137 3 1 Libraries 137 3 1 1 Configuration Library 137 3 1 2 USB Library 138 3 1 3 DMA Library 141 3 1 4 UART Library 142 3 1 5...

Page 7: ...6 Product Page Document Feedback Copyright 2015 Future Technology Devices International Limited 4 Contact Information 161 Appendix A References 162 Document References 162 Acronyms and Abbreviations...

Page 8: ...ave FT245 Parallel ADC Additional Timers The FT51A has an internal USB Full Speed device controller that is register compatible with an FT122 An internal on chip USB hub can optionally be enabled to a...

Page 9: ...62 Clearance No FTDI 483 8 Product Page Document Feedback Copyright 2015 Future Technology Devices International Limited The FT51A Tools are currently only available for Microsoft Windows and are test...

Page 10: ...n Table 2 1 SFRs 0x00 0x01 0x02 0x03 0x04 0x05 0x06 0x07 0x80 P0 SP DPL0 DPH0 DPL1 DPH1 DPS PCON 0x88 TCON TMOD TL0 TL1 TH0 TH1 CKCON 0x90 P1 EIF IO_DATA_9 0x98 SCON0 SBUF0 IO_ADDR_0 H IO_ADDR_0 L IO_...

Page 11: ...8051 SFR USB Device Hub Port SFR Table 2 2 FT51A Peripherals 2 1 1 Registers Accessed by SFR For peripherals and modules addressed directly through the SFRs the SDCC compiler provides a __sfr keyword...

Page 12: ...ress data IO_DATA_9 while 0 2 1 3 Register Descriptions The hardware and peripheral descriptions in this chapter include register maps which define the initial state of the registers their behaviour a...

Page 13: ...le of MTP memory 0x37 MTP_CRC_RESULT_L 16 bit CRC Result Lower Byte 0x38 MTP_CRC_RESULT_U 16 bit CRC Result Lower Byte 0x34 PIN_PACKAGE_CONFIG Device package Information 0x39 TOP_SECURITY_LEVEL Device...

Page 14: ...se a reset of the entire device This bit will always read as zero Table 2 5 Device Control Register The Device Control register provides top level write enable and reset functions for all top level re...

Page 15: ...suspend mode Table 2 6 System and Clock Divider Register Note When requesting a low power state and to obtain the lowest possible current consumption the User must ensure all pad IO controls have no p...

Page 16: ...ge speed as a modification of the clock divider bits during a UART operation will corrupt the data The switchback feature allows a system to burst to a faster mode when required by an external event E...

Page 17: ...Enable remote wakeup Hub will respond to a host get_status command with an ACK 0 Disable remote wakeup Hub will respond to a host get_status command with a STALL 3 hub_stsnzdatahsk R W 0 On receipt o...

Page 18: ...the memory contents have been successfully copied Write 1 to clear interrupt 1 dma0_irq R W1C 0 Set when the memory contents have been successfully copied Write 1 to clear interrupt 0 watchdog_irq R...

Page 19: ...to clear interrupt 5 pwm_irq R W1C 0 Set when the PWM has generated an interrupt Write 1 to clear interrupt 4 spi_slave_irq R W1C 0 Set when the SPI slave has generated an interrupt Write 1 to clear...

Page 20: ...pi_slave_irq_ien R W 0 Set to enable the SPI_SLAVE interrupt 3 spi_master_irq_ien R W 0 Set to enable the SPI_MASTER interrupt 2 uart_irq_ien R W 0 Set to enable the UART interrupt 1 io_cell_controlle...

Page 21: ...bit is cleared on completion of the copy 5 mtp_byte_prog_done R1C 0 Set when MTP BYTE write has completed See registers 0x2C 0x2D 0x2E Cleared upon reading Note This bit does NOT indicate completion o...

Page 22: ...DATA register will initiate the MTP byte write sequence It is advised to read the mtp_byte_prog_done register flag in MTP_CONTROL for completion Then the status of the write can then be read from the...

Page 23: ...48 44 32 or 28 pins This is a read only register that encodes the package type Bit Position Bit Field Name Type Reset Description 7 6 Pin Configuration R 0 7 6 Package pins 0 0 28 0 1 RFU 1 0 32 1 1...

Page 24: ...ector_3 R 0 Set to protect sector Start Address 0x2000 End Address 0x2FFF 0 Sector level is SL0 1 Sector level is SL1 1 Sector_2 R 0 Set to protect sector Start Address 0x1000 End Address 0x1FFF 0 Sec...

Page 25: ...ts are categorised as write forward as once a particular level has been set it is not possible to go back to a lower security level If the flash_mtp_mem operation is used then Shadow RAM byte 0x3FFF m...

Page 26: ...lines numbered 0 to 3 MOSI master out slave in MISO master in slave out The SPI Master protocol by default does not support any form of handshaking and the only available mode is unmanaged Data is clo...

Page 27: ...ata and transmission of output data is controlled by the SPI clock CLK An SPI transfer can only be initiated by the SPI Master and begins with the slave select signal SS being asserted by setting the...

Page 28: ...the SPI Master module The SPI Master module is enabled by setting the spi_master_dev_en bit to 1 Clearing this bit will disable the module To reset the module a 1 is written to the spi_master_soft_re...

Page 29: ...fer_size_done_int 4 rx_oe_ien R W 0 When set will enable rx_oe_int 3 rx_full_ien R W 0 When set will enable rx_full_int 2 tx_oe_ien R W 0 When set will enable tx_oe_int 1 tx_done_ien R W 0 When set wi...

Page 30: ...SPI_MASTER_RX_DATA has new data to be read out 2 tx_oe_int R W1C 0 Indicates a Tx overrun error when data is written to SPI_MASTER_TX_DATA while the register is still full If this occurs the old data...

Page 31: ...ter When transmitting data between SPI modules both modules must be using the same CPOL and CPHA values A change to either of these bits aborts a transmission in progress and returns the SPI system in...

Page 32: ...r Clock Divisor Register The SPI Master clock can operate up to one half of the CPU system clock CPU running at 48Mhz would set the SPI maximum clock to 24Mhz CPU running at 24Mhz would set the SPI ma...

Page 33: ...The SPI_MASTER_TRANSFER_SIZE register contains 16 bits and is split over 2 registers SPI_MASTER_TRANSFER_SIZE_L at 0x69 and SPI_MASTER_TRANSFER_SIZE_U at 0x6A Bit Position Bit Field Name Type Reset De...

Page 34: ...quired frequency of SCLK via the clock divisor in the SPI_MASTER_CLK_DIV register 4 Setup the SPI Master Mode and bit order as required in the SPI_MASTER_SETUP register 5 Leave the Slave Select line i...

Page 35: ...m the SPI slave To setup an interrupt routine Clear the tx_done_int bit in the SPI_MASTER_INT register Enable the interrupt in the tx_done_ien in the SPI_MASTER_IEN register Initialise the buffer to t...

Page 36: ...buf volatile uint8_t SPIM_MOSI_buf Initialise transfer WRITE_IO_REG 0x51 SPIM_MOSI_buf SPI_MASTER_DATA_TX_ADDR_1 SPIM_MOSI_buf Wait until all bytes have been sent by ISR while SPIM_num_bytes_tx 0 2 3...

Page 37: ...ve are outlined in Table 2 36 I O Address Register Name Description 0x48 SPI_SLAVE_CONTROL SPI Slave Control Register 0x4A SPI_SLAVE_DATA_TX Transmit data register 0x4B SPI_SLAVE_DATA_RX Receive data...

Page 38: ...ating whether the state machine is busy processing a transfer and a Tx done interrupt when a byte has been sent In the case of data to be received by the block there is a RX full interrupt indicating...

Page 39: ...Master 2 4 4 SPI_SLAVE_IEN Bit Position Bit Field Name Type Reset Description 7 5 RFU R 0 Reserved 4 rx_oe_ien R W 0 When set will enable rx_oe_int 3 rx_full_ien R W 0 When set will enable rx_full_int...

Page 40: ...new data to be read out 2 tx_oe_int R W1C 0 Indicates a Tx overrun error when data is written to the SPI_SLAVE_TX_DATA register while the register is still full If this occurs the old data is overwrit...

Page 41: ...ansmission in progress and returns the SPI system into an idle state Combined the CPOL and CPHA settings make 4 modes that are listed in Table 5 Mode 0 and 1 CPOL 0 the base inactive level of SCLK is...

Page 42: ...The registers associated with the I2 C Master are outlined in Table 2 44 These are accessed using SFRs directly SFR Address Register Name Description 0xF4 I2CMSA Slave Address register 0xF5 I2CMCR Con...

Page 43: ...tion Bit Field Name Type Reset Description 7 RSTB W1T 0 Triggers a reset of the I2 C Master module 6 SLRST W1T 0 Performs a slave reset 5 ADDR W1T 0 Slave Address 4 HS W1T 0 High speed mode 3 ACK W1T...

Page 44: ...R 0 Indicates that due to the last operation the transmitted data was not acknowledged 2 ADDR_ACK R 0 Indicates that due to the last operation the slave address was not acknowledged 1 ERROR R 0 Indica...

Page 45: ...vant I2 C mode STANDARD FAST FAST PLUS HIGH SPEED depending on the SCL frequency calculated The maximum frequency is limited to the lesser of one tenth of the system clock frequency or 3 400 000Hz Thi...

Page 46: ...0 STOP 0 START 1 RUN 1 Read the I2CMSR register until the BUSY bit is clear o Write the last byte of data to the I2CMBUF register o Write to the Control Register I2CMCR with HS 0 STOP 1 START 1 RUN 1...

Page 47: ...yte of data from the I2CMBUF register o Write to the Control Register I2CMCR with HS 0 ACK 0 STOP 1 START 1 RUN 1 o Read the I2CMSA register until the BUSY bit is clear o Read the last byte of data fr...

Page 48: ...acknowledge a read to the master only when data has been written to the I2 C Slave data register Likewise the I2 C Slave will not acknowledge a write by the master until data has been read from the I2...

Page 49: ...RECFINCLR W 0 Clear RECFIN bit in I2CSSR register 2 SENDFINCLR W 0 Clear SENDFIN bit in I2CSSR register 1 0 Reserved RFU 0 Reserved Table 2 52 I2 C Slave Control Register The I2 C Slave Control regis...

Page 50: ...gister when RREQ is set will acknowledge a transmission from the I2 C Master 2 6 5 Use Case The I2 C Slave can process single bytes or bursts of an indeterminate length from the I2 C Master The interr...

Page 51: ...Receive Data To receive data from an I2 C Master the following procedure is used For each byte of data o If I2CSCR register bit RREQ set to 1 Read byte of data from I2CSBUF o If I2CSCR register bit R...

Page 52: ...OL UART control register 0x61 UART_DMA_CTRL UART DMA control register 0x62 UART_RX_DATA UART Receive Data register 0x63 UART_TX_DATA UART Transmit Data register 0x64 UART_TX_IEN UART Tx Status Enable...

Page 53: ...e the module To reset the module a 1 is written to the uart_soft_reset bit This is cleared when the reset is performed and will therefore always read as 0 2 7 2 UART_DMA_CTRL Bit Position Bit Field Na...

Page 54: ...hold_txe_ien R W 0 Interrupt enable bit for hold_txe_int Table 2 60 UART Transmit Status Interrupt Enable Register 2 7 6 UART_TX_INT Bit Position Bit Field Name Type Reset Description 7 Reserved RFU...

Page 55: ...nt interrupt Table 2 62 UART Receive Status Interrupt Enable Register 2 7 8 UART_RX_INT Bit Position Bit Field Name Type Reset Description 7 5 Reserved RFU 0 Reserved 4 break_rcvd_int R W 0 The interr...

Page 56: ...g UART Clear this bit to disable the break 4 2 parity_sel R W 0 Parity Sel Bits Parity xx0 No Parity 001 Odd Parity Parity bit will be set to a 1 or 0 to ensure an odd number of 1s are sent 011 Even P...

Page 57: ...ription 7 0 uart_baud_1 R W 0x13 Middle byte of the baud rate setting Table 2 66 UART Baud Rate 1 Register Bit Position Bit Field Name Type Reset Description 7 Reserved RFU 0 Reserved 6 4 uart_baud_fr...

Page 58: ...x00 respectively This will set the baud rate divisor to be 0x1388 or 5000dec The final baud rate will be 48000000 5000 9600 baud Figure 2 5 UART Baud Rate Example Calculations 2 7 12 UART_FLOW_CTRL Bi...

Page 59: ...ices International Limited 2 7 13 UART_FLOW_STAT Bit Position Bit Field Name Type Reset Description 7 4 Reserved RFU 0 Reserved 3 ri_reg RO 0 Status of the Ring Indicator signal 2 dcd_reg RO 0 Status...

Page 60: ...ter as shown in Table 2 70 I O Address Register Name Description 0x1A DIGITAL_CONTROL_GPIO_0 Control register for DIO 0 0x1B DIGITAL_CONTROL_GPIO_1 Control register for DIO 1 0x1C DIGITAL_CONTROL_GPIO...

Page 61: ...e 2 puena R W 0 Pull up Enable When this signal is set a weak internal pull up is enabled to hold the pad in a high logic state if the pad is left unconnected or tri state 1 0 drive_strength R W 0 Dri...

Page 62: ...L_AIO_5 Control register for AIO 5 in digital mode 0x10 DIGITAL_CONTROL_AIO_6 Control register for AIO 6 in digital mode 0x11 DIGITAL_CONTROL_AIO_7 Control register for AIO 7 in digital mode 0x12 DIGI...

Page 63: ...k internal pull down is enabled to hold the pad in a low logic state if the pad is left unconnected or tri state 2 puena R W 0 Pull up Enable When this signal is set a weak internal pull up is enabled...

Page 64: ...7 respectively The registers associated with the IOMUX are outlined in Table 2 74 I O Address Register Name Description 0x40 IOMUX_CONTROL Used to enable and reset the IOMUX 0x41 IOMUX_OUTPUT_PAD_SEL...

Page 65: ...2 9 3 IOMUX_OUTPUT_SIG_SEL Bit Position Bit Field Name Type Reset Description 7 0 op_sig_sel R W 0x00 Signal to be used for an output mapping Table 2 77 IOMUX Output Signal Select Register This descri...

Page 66: ...9 IOMUX Input Pad Select Register This register selects the input pad for a signal mapping The pad is selected from Table 2 80 Note that the values in Table 2 80 are decimal values When this register...

Page 67: ...DIO_1 17 AIO_2 2 DIO_2 18 AIO_3 3 DIO_3 19 AIO_4 4 DIO_4 20 AIO_5 5 DIO_5 21 AIO_6 6 DIO_6 22 AIO_7 7 DIO_7 23 AIO_8 8 DIO_8 24 AIO_9 9 DIO_9 25 AIO_10 10 DIO_10 26 AIO_11 11 DIO_11 27 AIO_12 12 DIO_1...

Page 68: ...71 SPI_MASTER_SCLK 28 GPIO_PORT2O_6 70 SPI_MASTER_MISO_ LOOPBACK 27 GPIO_PORT2O_5 69 SPI_MASTER_MOSI 26 GPIO_PORT2O_4 68 CLKOUT 25 GPIO_PORT2O_3 67 SUSPEND_OPEN_DRAIN 24 GPIO_PORT2O_2 66 SUSPEND 23 G...

Page 69: ...45_DATA_WRITE_1 29 I2C_MASTER_SCL 59 FIFO_245_DATA_WRITE_0 28 HUB_P2_OVER_CURRENT 58 I2C_SDA 27 HUB_P1_OVER_CURRENT 57 I2C_SCL 26 GPIO_PORT3I_7 56 SPI_SLAVE_SS_N 25 GPIO_PORT3I_6 55 SPI_SLAVE_SCLK 24...

Page 70: ...different pads It should be noted that the IOMUX mapping MUST be performed during configuration of the device and not while the signals being mapped are active 2 9 9 1 Setup an Input Signal To progra...

Page 71: ...ashion to Digital ports See Section 2 8 2 ADC Where the pad is an input and can be sampled to perform analogue to digital conversion A special Global Mode is implemented to allow multiple ADC conversi...

Page 72: ...ssively approximate in hardware the output of a sample and hold circuit Physically there are four DACs each shared by four AIO ports as illustrated below Figure 2 6 Pad Distribution 2 10 3 AIO Configu...

Page 73: ...2 86 AIO Mode Control Register Addresses mode1 mode0 Configuration 0 0 Analogue off Pad configured for Digital Mode 0 1 Reserved 1 0 ADC Mode 1 1 Reserved Table 2 87 AIO Mode Control Bits 2 10 3 1 AIO...

Page 74: ...O_MODE_2 Bit Position Bit Field Name Type Reset Description 7 6 AIO_11_MODE R W 0 Analogue mode of operation for AIO_11 port See Table 2 87 5 4 AIO_10_MODE R W 0 Analogue mode of operation for AIO_10...

Page 75: ...ital representation of the wave The AIO_SAMPLE_0 and AIO_SAMPLE_1 registers determine which AIO ports shall be sampled by the analogue to digital convertor Once the conversion is completed the interru...

Page 76: ...AIO_4 ADC data 0x148 0x149 AIO_5_ADC_DATA_L AIO_5_ADC_DATA_U Lower byte of AIO_5 ADC data Upper 2 bits of AIO_5 ADC data 0x14A 0x14B AIO_6_ADC_DATA_L AIO_6_ADC_DATA_U Lower byte of AIO_6 ADC data Upp...

Page 77: ...AIO_6_SAMPLE W 0 Sample AIO_6 port 5 AIO_5_SAMPLE W 0 Sample AIO_5 port 4 AIO_4_SAMPLE W 0 Sample AIO_4 port 3 AIO_3_SAMPLE W 0 Sample AIO_3 port 2 AIO_2_SAMPLE W 0 Sample AIO_2 port 1 AIO_1_SAMPLE W...

Page 78: ...mple Result Lower Registers 2 10 4 4 AIO_x_ADC_DATA_U Bit Position Bit Field Name Type Reset Description 7 2 Reserved RFU 0 Always reads as zero 1 0 UPPER DATA R 0 Digital representation of the analog...

Page 79: ...complete for that particular Analogue Cell 6 AIO_6_INT RO 0 5 AIO_5_INT RO 0 4 AIO_4_INT RO 0 3 AIO_3_INT RO 0 2 AIO_2_INT RO 0 1 AIO_1_INT RO 0 0 AIO_0_INT RO 0 Table 2 98 AIO Interrupts 0 7 Registe...

Page 80: ...T_ENABLES_8_15 Bit Position Bit Field Name Type Reset Description 7 AIO_15_IEN RW 0 Interrupt Enable bit Write a 1 to enable the corresponding interrupt bit in register AIO_INTERRUPTS_8_15 6 AIO_14_IE...

Page 81: ...Reserved 5 global_update_ien R W 0 Write 1 to enable the Global Update interrupt bit global_update_int 4 global_update_int R W1C 0 Global Update Interrupt bit Set when ADC data has been transferred fr...

Page 82: ..._PORT_SELECT_8_15 Bit Position Bit Field Name Type Reset Description 7 aio_port_15_active R W 0 Write 1 to include Port in Global List 6 aio_port_14_active R W 0 Write 1 to include Port in Global List...

Page 83: ...2 For this shared DAC use no more than two ports in Global mode AIO_9 DAC_2 AIO_10 DAC_2 AIO_11 DAC_2 AIO_12 DAC_3 For this shared DAC use no more than two ports in Global mode AIO_13 DAC_3 AIO_14 DAC...

Page 84: ..._8_9 R W 0 Write 1 to configure AIO Pads 8 and 9 as a differential pair 3 diff_6_7 R W 0 Write 1 to configure AIO Pads 6 and 7 as a differential pair 2 diff_4_5 R W 0 Write 1 to configure AIO Pads 4 a...

Page 85: ...te to this register to divide the system clock supplied to the AIO Module The divided clock is used to determine the delays applied based on the above registers Table 2 108 AIO Settling Times Register...

Page 86: ...ns Therefore the allowed Sample Hold settling time will be 567 20 83 11 8 us For optimal ADC performance it is recommended that the AIO_SH_COUNTER default value of 0x139 is overwritten with 0x237 i e...

Page 87: ...or more details Write to the AIO_GLOBAL_CTRL registers to select which cells are to be included in global sample Write to the appropriate mode register AIO_MODE_0 AIO_MODE_1 AIO_MODE_2 AIO_MODE_3 to s...

Page 88: ...r management schemes are different in these two modes Upon reset the default mode is functional The enhanced mode is activated when any of the Set Endpoint Configuration commands 0xB0 to 0xBF is recei...

Page 89: ...USB Full Speed device controller 2 11 1 2 Endpoint Buffer Management in Enhanced Mode In enhanced mode the USB Full Speed device controller supports a dedicated 1 kB buffer for IN packets and a dedic...

Page 90: ...ation 0 Configuration 1 Configuration 2 EP Buffer EP Buffer EP Buffer 7 1 7 ISO 1 128 bytes 5 ISO 1 448 bytes 7 0 6 1 7 ISO 0 128 bytes 6 0 5 1 6 1 5 0 6 0 4 1 2 1 4 0 2 0 5 ISO 0 448 bytes 3 1 1 ISO...

Page 91: ...y Non isochronous endpoint Isochronous endpoint 0000 8 bytes 16 bytes 0001 16 bytes 32 bytes 0010 32 bytes 48 bytes 0011 64 bytes 64 bytes 0100 96 bytes 0101 128 bytes 0110 160 bytes 0111 192 bytes 10...

Page 92: ...2 OUT 0x04 Read 1 byte optional Endpoint 2 IN 0x05 Read 1 byte optional Read Last Transaction Status Endpoint 0 OUT 0x40 Read 1 byte Endpoint 0 IN 0x41 Read 1 byte Endpoint 1 OUT 0x42 Read 1 byte End...

Page 93: ...92 Product Page Document Feedback Copyright 2015 Future Technology Devices International Limited Command Name Target Code hex Data phase Validate Buffer Selected Endpoint 0xFA None General Commands Re...

Page 94: ...t 3 IN 0xB7 Write 1 byte Endpoint 4 OUT 0xB8 Write 1 byte Endpoint 4 IN 0xB9 Write 1 byte Endpoint 5 OUT 0xBA Write 1 byte Endpoint 5 IN 0xBB Write 1 byte Endpoint 6 OUT 0xBC Write 1 byte Endpoint 6 I...

Page 95: ...7 Read 1 byte Endpoint 4 OUT 0x48 Read 1 byte Endpoint 4 IN 0x49 Read 1 byte Endpoint 5 OUT 0x4A Read 1 byte Endpoint 5 IN 0x4B Read 1 byte Endpoint 6 OUT 0x4C Read 1 byte Endpoint 6 IN 0x4D Read 1 by...

Page 96: ...e 1 byte Endpoint 2 IN 0x45 Write 1 byte Endpoint 3 OUT 0x46 Write 1 byte Endpoint 3 IN 0x47 Write 1 byte Endpoint 4 OUT 0x48 Write 1 byte Endpoint 4 IN 0x49 Write 1 byte Endpoint 5 OUT 0x4A Write 1 b...

Page 97: ...e address A bus reset will reset all address bits to 0 7 Enable 0 Function enable A bus reset will automatically enable the function at default address 0 Table 2 119 Address Enable Register 2 11 3 2 S...

Page 98: ...pend current requirement Note The programmed value is not changed by a bus reset 3 Interrupt Mode 1 0 an interrupt will not be generated on NAK or Error transactions 1 an interrupt will be generated o...

Page 99: ...value is not be changed by a bus reset 5 4 Reserved 0 Reserved write to 0 6 SET_TO_ONE 0 This bit must be set to 1 7 SOF only Interrupt Mode 0 0 normal operation 1 interrupt will generate on receiving...

Page 100: ...ndpoint 1 OUT buffer Cleared by Read Last Transaction Status command 3 Endpoint 1 In 0 Interrupt for endpoint 1 IN buffer Cleared by Read Last Transaction Status command 4 Endpoint 2 Out 0 Interrupt f...

Page 101: ...Read Last Transaction Status command 4 Endpoint 5 Out 0 Interrupt for endpoint 5 OUT buffer Cleared by Read Last Transaction Status command 5 Endpoint 5 In 0 Interrupt for endpoint 5 IN buffer Cleared...

Page 102: ...0 Reserved Table 2 128 Endpoint Status Register 2 11 4 3 Read Last Transaction Status Command 0x40 0x45 0x40 0x4F for Enhanced Mode Data Read 1 byte Bit Symbol Reset Description 0 Data Receive Transm...

Page 103: ...ure Technology Devices International Limited Error Code Result 0000 No error 0001 PID encoding error 0010 PID unknown 0011 Unexpected packet 0100 Token CRC error 0101 Data CRC error 0110 Time out erro...

Page 104: ...Endpoint Stalled 0 0 endpoint is not stalled 1 endpoint is stalled Table 2 131 Endpoint Buffer Status Register 2 11 4 5 Read Buffer Command 0xF0 Data Read multiple bytes The Read Buffer command is use...

Page 105: ...40 0x45 0x40 0x4F for Enhanced Mode Data Write 1 byte Bit Symbol Reset Description 0 Stall 0 0 Disable the endpoint STALL state 1 Enable the endpoint STALL state For EP0 OUT control OUT endpoint the S...

Page 106: ...ms If the clock is not running during suspend the MCU needs to wakeup FT122USB Full Speed device controller by drive SUSPEND pin to LOW followed by Send Resume command 2 11 5 3 Set Buffer Interrupt Mo...

Page 107: ...also consists of an output control block which enables PWM outputs once twice 255 times forever and generates an interrupt The registers associated with the Pulse Width Modulation PWM are outlined be...

Page 108: ...out toggle enable register 5 0x9B PWM_OUT_TOGGLE_EN_6 PWM out toggle enable register 6 0x9C PWM_OUT_TOGGLE_EN_7 PWM out toggle enable register 7 0x9D PWM_OUT_CLR_EN PWM out clear enable register 0x9E...

Page 109: ...a method that can be used to interface to analogue hardware using a digital source such as a microcontroller Real world applications of PWM include lamp brightness electric motor control and servo co...

Page 110: ...block Table 2 137 PWM Ctrl 1 Register This register allows enabling and detecting PWM interrupt PWM busy and setting up the trigger edge 2 12 3 PWM_PRESCALER Bit Position Bit Field Name Type Reset Des...

Page 111: ...hannel determines the toggle events up to 8 which give up to 4 data pulses Simple duty cycle based pulse width modulation can be programmed with only two comparators There are a total of 8 comparators...

Page 112: ...mes Table 2 145 PWM Control Block Register This controls the number of times to repeat the PWM waveform The control block is shared across all 8 PWM channels 2 12 11 PWM_INIT Bit Position Bit Field Na...

Page 113: ...12 clocks 12 24 This produces a 50 duty cycle By programming different toggling values into the FT51A comparators a wide range of duty cycles can be generated First parameter to decide on is the frequ...

Page 114: ...48MHz PWM Counter 1 PWM Pulse Duration 20ns 2a assuming the 48MHz FT51A Clock Set the PWM Clock to its minimum value of 187 5kHz assuming the 48MHz FT51A Clock and increment PWM counter by 65535 to g...

Page 115: ...REG 0x86 0x00 PWM_CMP16_0_MSB WRITE_IO_REG 0x85 0x00 PWM_CMP16_0_LSB Set PWM Comparator 1 WRITE_IO_REG 0x88 0xAA PWM_CMP16_1_MSB WRITE_IO_REG 0x87 0xFF PWM_CMP16_1_LSB Set toggle enables for the two c...

Page 116: ...onfigured to be in one shot or in continuous mode They are initialised from a common register set so only one may be initialised at a time multiplexed access The FTDI watchdog timer is clocked off the...

Page 117: ...r start value 0x79 TIMER_WRITE_MS Timer start value 0x7A TIMER_PRESC_LS Timer pre scale value 0x7B TIMER_PRESC_MS Timer pre scale value 0x7C TIMER_READ_LS Timer read value 0x7D TIMER_READ_MS Timer rea...

Page 118: ...the timer B 0 start_A W1T 0 Start the timer A Table 2 152 Timer Control 1 Register 2 13 3 TIMER_CONTROL_2 Bit Position Bit Field Name Type Reset Description 7 4 prescaler_en R W 0 Enable pre scaler b...

Page 119: ...Timer C 1 clear_B W1T 0 Clear Timer B 0 clear_A W1T 0 Clear Timer A Table 2 155 Timer Control 3 Register 2 13 6 TIMER_INT Bit Position Bit Field Name Type Reset Description 7 timer_int_D_ien R W 0 Ti...

Page 120: ...ontrol 3 Register 2 13 8 TIMER_WDG Bit Position Bit Field Name Type Reset Description 4 0 timer_wdg_write R W 0 Watchdog bit position to initialise Table 2 158 Timer Watchdog Register 2 13 9 TIMER_WRI...

Page 121: ...me Type Reset Description 7 0 timer_presc_15_8 R W 0 Bits 15 to 8 of the pre scale value Table 2 162 Timer Prescaler MSB Register 2 13 13 TIMER_READ_LS Bit Position Bit Field Name Type Reset Descripti...

Page 122: ...rection field to select up down counting N A N A Write into TIMER_CTRL_3 register mode field to select mode N A N A Write bit for selected timer to TIMER_CTRL_4 register to initialise the timer Write...

Page 123: ...er 0 versus the FTDI Timer A Standard 8051 Timer 0 Set the Timer 0 prescaler to 0 0 divide by 12 1 divide by 4 Note CKCON bit 3 relates to Timer 0 bit 4 Timer 1 CKCON 0xF7 Set timer control mode eithe...

Page 124: ...MER_CONTROL_2 PRESCALER_EN_0 Start timer A WRITE_IO_REG 0x71 0x01 TIMER_CONTROL_1 START_A FTDI Timers A B C and D require 1 cycle per instruction whereas standard timers 0 1 or 2 require either 12 def...

Page 125: ...Timer range for uint32_t timer 2 13 15 2 Watchdog Software must feed the watchdog within a set period as determined by the timer_wdg_write bit of the TIMER_WDG register to verify proper software execu...

Page 126: ...rief Explains the cause of the most recent reset typedef enum Power supply was removed or interrupted NORMAL_RESET Watchdog was not fed in time WATCHDOG_RESET RESET_REASON brief Reset cause details A...

Page 127: ...N reset_reason WATCHDOG_RESET int i Once the cause of the reset is known the behaviour of the app can be changed accordingly reset_cause reset_reason if reset_reason WATCHDOG_RESET Write code to do so...

Page 128: ...A source memory address LSB register 0xB5 DMA_SRC_MEM_ADDR_U_1 IO Peripheral DMA source memory address MSB register 0xB6 DMA_DEST_MEM_ADDR_L_1 IO Peripheral DMA destination memory address LSB register...

Page 129: ...DMA destination memory address MSB register 0xC8 DMA_IO_ADDR_L_2 IO Peripheral DMA IO Address LSB Register 0xC9 DMA_IO_ADDR_U_2 IO Peripheral DMA IO Address MSB Register 0xCA DMA_TRANS_CNT_L_2 IO Per...

Page 130: ...MA_TRANS_CNT_U_3 IO Peripheral DMA Transfer Byte Count MSB Register 0xDC DMA_CURR_CNT_L_3 IO Peripheral DMA Current Transfer Byte Count LSB Register 0xDD DMA_CURR_CNT_U_3 IO Peripheral DMA Current Tra...

Page 131: ...rent Transfer Byte Count MSB Register 0xEE DMA_FIFO_DATA_4 IO Peripheral DMA FIFO DATA 0xEF DMA_AFULL_TRIGGER_4 IO Peripheral DMA Almost Full Trigger Value Table 2 167 DMA Register Addresses 2 14 1 DM...

Page 132: ...ter 2 14 3 DMA_IRQ_ENA_x Bit Position Bit Field Name Type Reset Description 7 Reserved RFU 0 Reserved 6 5 dma_fifo_size R W 0 IO Peripheral DMA Set FIFO Size 00 64 01 128 10 256 11 512 Bytes 4 3 dma_m...

Page 133: ...RC_MEM_ADDR_L_x Bit Position Bit Field Name Type Reset Description 7 0 dma_src_mem_addr_l R W 0 IO Peripheral DMA Source Memory Address Register 7 0 Table 2 172 IO Peripheral DMA Source Memory Address...

Page 134: ...Memory Address Register 14 8 Table 2 175 IO Peripheral DMA Destination Memory Address MSB Register 2 14 9 DMA_IO_ADDR_L_x Bit Position Bit Field Name Type Reset Description 7 0 dmaio_io_addr_l R W 0 I...

Page 135: ...eral DMA Transfer Byte Count Register 13 8 Table 2 179 IO Peripheral DMA Transfer Byte Count MSB Register 2 14 13 DMA_CURR_CNT_L_x Bit Position Bit Field Name Type Reset Description 7 0 dma_curr_cnt_l...

Page 136: ...EG DMA_IRQ_ENA_1 DMA0_IRQ_IEN 3 Enable individual DMA engine WRITE_IO_REG DMA_CONTROL_1 DMA_CONTROL_0_DEV_EN 4 Enable interrupts for the Push mode WRITE_IO_REG DMA_IRQ_ENA_1 DMA_IRQ_DONE_IEN 0 MASK_DM...

Page 137: ...at engine interrupted void INT0_ISR void __interrupt 0 uint8_t events 0 READ_IO_REG TOP_INT0 events events DMA0_IRQ DMA1_IRQ DMA2_IRQ DMA3_IRQ if events DMA0_IRQ NULL user_callback Clear the event fla...

Page 138: ...which are not called but will not normally optimize out unused functions within files This reduces code size in an application without requiring manual examination of calling graphs The intention is...

Page 139: ...s via the call back functions This allows the call backs to be run by the application and not at interrupt level Non control endpoints must be created by a call to USB_create_endpoint before being use...

Page 140: ...ent configuration for the GET_CONFIGURATION request to the host This is a standard request and this function is called from the standard request call back function 3 1 2 5 USB_clear_endpoint File ft51...

Page 141: ...f the USB Specifications 3 1 2 12 USB_set_state File ft51_usb_state c Calling this function will set the current state of the USB device This is defined in Section 9 1 of the USB Specifications 3 1 2...

Page 142: ...set a DMA engine to run to complete the transfer As this does not block until completion the DMA_wait_on_complete call is used to wait until the transfer is finished When the DMA engine is no longer r...

Page 143: ..._switch _fifo c Change the destination buffer of a FIFO 3 1 3 12 DMA_is_complete File ft51_dma_is_complete c Checks whether a DMA is complete 3 1 3 13 DMA_release File ft51_dma_release c Requires ft51...

Page 144: ...checking on the UART 3 1 4 6 UART_set_stop_bits File ft51_uart_set_stop_bits c Set the number of stop bits in a UART character to 1 or 2 3 1 4 7 UART_read File ft51_uart_read c Read a number of bytes...

Page 145: ...r to use DMA It requires that the DMA library is included 3 1 5 5 SPIM_transceive_DMA File ft51_spim_transceive_dma c Requires ft51_dma_configure c ft51_dma_enable c ft51_dma_wait_on_complete c A tran...

Page 146: ...a to an I2 C Master It is possible to use interrupt methods to perform both reads and write This is not implemented in this library Source Folder i2c 3 1 7 1 I2C_slave_initialise File ft51_i2c_slave c...

Page 147: ...9 2 IOMUX_INPUT This is a macro to connect a pad to a signal to receive data for a peripheral 3 1 9 3 IOMUX_OUTPUT This is a macro to connect a signal to a pad to transmit data from a peripheral 3 1...

Page 148: ...ributes will need to be set to 0 for no It supports downloading of firmware only bitCanDnload but does not support manifest checking bitManifestationTolerant This library is in a single file Source Fo...

Page 149: ...aracters set the bias and contrast cursor off and blink off clear the display and set the entry mode 3 1 12 2 lcd_clear Send the clear command to remove text from the display 3 1 12 3 lcd_home Move th...

Page 150: ...it_abort_bulk_out Aborts a Bulk OUT transfer This may be a Message Out or a Request Message In INITIATE_ABORT_BULK_OUT 3 1 13 6 tmc_class_check_abort_bulk_out Returns the status of a previously sent I...

Page 151: ...callback functions for standard SETUP requests from the host Call the USB_process function periodically If vendor or class SETUP requests are required by the host driver then additional handlers must...

Page 152: ...are copied to the __data or __xdata areas This will use memory resources Typically the descriptors will not be changed by an application 3 2 2 1 Device Descriptors The device descriptor uses USB_devic...

Page 153: ...Endpoints 0x01 interface bInterfaceClass USB_CLASS_HID interface bInterfaceSubClass 1 interface bInterfaceProtocol 1 interface iInterface 0x05 HID DESCRIPTOR for Keyboard hid bLength 0x09 hid bDescrip...

Page 154: ...The reason for this is to allow tools to edit the string descriptors The ft51str exe tool can edit string descriptors during the process of programming the device allowing unique serial numbers or ot...

Page 155: ...n will cause a stall on the control endpoint to signal to the host that the SETUP request failed 3 2 3 1 Get Status The minimum requirement for a response to the standard request GET_STATUS is for end...

Page 156: ...dir LSB req wIndex 7 USB_STATE state USB_get_state if req bmRequestType USB_BMREQUESTTYPE_DIR_DEV_TO_HOST USB_BMREQUESTTYPE_RECIPIENT_ENDPOINT Only support the endpoint halt feature in this device if...

Page 157: ...device_descriptor if length sizeof USB_device_descriptor too many bytes requested length sizeof USB_device_descriptor Entire structure break break case USB_DESCRIPTOR_TYPE_CONFIGURATION src char conf...

Page 158: ...the interface number is correct if req bmRequestType USB_BMREQUESTTYPE_RECIPIENT_MASK USB_BMREQUESTTYPE_RECIPIENT_INTERFACE Handle HID class requests switch req bRequest case USB_HID_REQUEST_CODE_SET...

Page 159: ...is self powered and is disconnected from the host Any special programming required to handle suspend states should be placed in here 3 2 5 3 Resume Call back The resume call back is used when either t...

Page 160: ...cies Instead of latencies in excess of 20 ms it ensures transitions in tens of microseconds and leaves it up to the user to decide if to reduce the power or not The host or hub initiates entry to L1 b...

Page 161: ...o L1 Sleep if first_time first_time 0 FT122_CMD READ_LPM_STATUS lpm_status 0 FT122_DATA lpm_status 1 FT122_DATA void process_setup_packet void called from USB_process USB_request_callback cb NULL uint...

Page 162: ...Site http ftdichip com Distributor and Sales Representatives Please visit the Sales Network page of the FTDI Web site for the contact details of our distributor s and sales representative s in your c...

Page 163: ..._Measur ement_Sample pdf AN_348 FT51A FT800 Sensors Sample http www ftdichip com Support Documents AppNotes AN_348_FT51A_FT800_Sensors_S ample pdf AN_349 FT51A FT800 Spaced Invaders Sample http www ft...

Page 164: ...t Feedback Copyright 2015 Future Technology Devices International Limited Acronyms and Abbreviations Terms Description USB Universal Serial Bus USB IF USB Implementers Forum MTP Multiple Time Program...

Page 165: ...e 2 14 MTP Address Lower Register 20 Table 2 15 MTP Address Upper Register 21 Table 2 16 MTP Data Register 21 Table 2 17 MTP CRC Control Register 21 Table 2 18 MTP CRC Result Lower Register 21 Table 2...

Page 166: ...C Slave Address Register 47 Table 2 52 I2 C Slave Control Register 48 Table 2 53 I2 C Slave Status Register 49 Table 2 54 I2 C Slave Data Buffer Register 49 Table 2 55 UART Register Addresses 51 Tabl...

Page 167: ...ol 3 Register 73 Table 2 92 AIO ADC Register Addresses 76 Table 2 93 AIO ADC Sample Select 0 Register 76 Table 2 94 AIO ADC Sample Select 1 Register 76 Table 2 95 AIO ADC Sample Result Lower Registers...

Page 168: ...Register 101 Table 2 129 Endpoint Last Transaction Status Register 101 Table 2 130 Transaction error code 102 Table 2 131 Endpoint Buffer Status Register 103 Table 2 132 Endpoint Control Register 104...

Page 169: ...errupts Enable Register 131 Table 2 171 DMA Interrupts Register 132 Table 2 172 IO Peripheral DMA Source Memory Address LSB Register 132 Table 2 173 IO Peripheral DMA Source Memory Address MSB Registe...

Page 170: ...FTDI 483 169 Product Page Document Feedback Copyright 2015 Future Technology Devices International Limited Figure 2 7 Square wave with 50 duty cycle 107 Figure 2 8 Square wave with 20 duty cycle 108...

Page 171: ...nt Feedback Copyright 2015 Future Technology Devices International Limited Appendix C Revision History Document Title AN_289 FT51A Programming Guide Document Reference No FT_000962 Clearance No FTDI 4...

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