FTDI FT51A, Application Note

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Application Note
AN_289 FT51A Programming Guide
Version 1.0
Document Reference No.: FT_000962 Clearance No.: FTDI# 483
47
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2.6 I
2
C Slave
The I
2
C Slave is an industry standard communications interface. Devices communicate in Master or
Slave mode, with the Master initiating the data transfer.
The I
2
C Slave module has two signals:
- Clock (SCL)
- Data (SDA)
The I
2
C Slave responds to an address transmitted by the I
2
C Master that prefixes any data
transferred. The Least Significant Bit of the address specifies Read or Write operation.
The I
2
C Slave is a polled interface. It will return data and acknowledge a read to the master only
when data has been written to the I
2
C Slave data register. Likewise, the I
2
C Slave will not
acknowledge a write by the master until data has been read from the I
2
C Slave data register.
Figure 2.4 I
2
C Slave Schematic Diagram
The registers associated with the I
2
C Slave are outlined in Table 2.50. These are accessed using
SFRs directly.
SFR
Address
Register Name Description
0xF1
I2CSOA
Own Address register.
0xF2
I2CSCR
Control register (write operation).
0xF2
I2CSSR
Status register (read operation).
0xF3
I2CSBUF
Transmitted/received data
register.
Table 2.50 I
2
C Slave Register Addresses
2.6.1 I2CSOA
Bit
Position
Bit Field Name Type Reset Description
7 Reserved RFU 0 Reserved
6..0
addr
R/W 0
Own address bits 7..1. Note that own
address bit zero indicates direction.
Table 2.51 I
2
C Slave Address Register
External -
I2C Master
I2C Slave
SCL
SDA