FTDI FT51A, Application Note

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Application Note
AN_289 FT51A Programming Guide
Version 1.0
Document Reference No.: FT_000962 Clearance No.: FTDI# 483
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2.10.5.3 AIO_INTERRUPT_ENABLES_0_7
Bit
Position
Bit Field Name Type Reset Description
7
AIO_7_IEN
RW 0
Interrupt Enable bit.
Write a 1 to enable the corresponding
interrupt bit in register
AIO_INTERRUPTS_0_7
6
AIO_6_IEN
RW 0
5
AIO_5_IEN
RW 0
4
AIO_4_IEN
RW 0
3
AIO_3_IEN
RW 0
2
AIO_2_IEN
RW 0
1
AIO_1_IEN
RW 0
0
AIO_0_IEN
RW 0
Table 2.100 AIO Interrupt Enables 0-7 Register
2.10.5.4 AIO_INTERRUPT_ENABLES_8_15
Bit
Position
Bit Field Name Type Reset Description
7
AIO_15_IEN
RW 0
Interrupt Enable bit.
Write a 1 to enable the corresponding
interrupt bit in register
AIO_INTERRUPTS_8_15
6
AIO_14_IEN
RW 0
5
AIO_13_IEN
RW 0
4
AIO_12_IEN
RW 0
3
AIO_11_IEN
RW 0
2
AIO_10_IEN
RW 0
1
AIO_9_IEN
RW 0
0
AIO_8_IEN
RW 0
Table 2.101 AIO Interrupt Enables 8-15 Register
2.10.6 Global Mode
Global mode allows multiple ADC ports to be sampled simultaneously, i.e. there is no need to
assert each individual sample bit. Any ADCs that are selected to be in Global mode will be
sampled when the Global Sample bit is asserted.
For ports that are in ADC mode, Global Update must be asserted in order to transfer the results to
the ADC Data registers once the sample is complete.
The following registers are used in Global Mode.