Application Note
AN_289 FT51A Programming Guide
Version 1.0
Document Reference No.: FT_000962 Clearance No.: FTDI# 483
35
Copyright © 2015 Future Technology Devices International Limited
SPIM_M+;
WRITE_IO_REG(0x54, 0x1<<3); //Clear RX_FULL interrupt
}
if(SPIM_interrupt & 0x1) // Check for TX_HOLD interrupt
{
if(SPIM_num_bytes_tx > 1)
{
WRITE_IO_REG(0x51, *SPIM_MOSI_buf); //SPI_MASTER_DATA_TX_ADDR_1
SPIM_M+;
}
WRITE_IO_REG(0x54, 0x1); //Clear TX_HOLD interrupt
}
}
//It is up to the user to define the variables,
//initialise transfer and check if all bytes have been sent as follows:
//Variables
volatile uint8_t
SPIM_interrupt;
volatile uint16_t
SPIM_num_bytes_tx;
volatile uint8_t
*SPIM_MISO_buf;
volatile uint8_t
*SPIM_MOSI_buf;
//Initialise transfer
WRITE_IO_REG(0x51, *SPIM_MOSI_buf); //SPI_MASTER_DATA_TX_ADDR_1
SPIM_M+;
//Wait until all bytes have been sent by ISR
while(SPIM_num_bytes_tx != 0);
2.3.12.4
DMA Interface
Data transfers can also be controlled by DMA. Below is the sequence of steps required to control
transfer via DMA. Additional details on how to configure DMAs can be found in the DMA section of
this document.
1.
Initialise DMA;
2.
Acquire DMA PUSH (Tx) and PULL (Rx) engines;
3.
Configure DMA source, destination, data size, mode and function;
4.
Activate Slave Select;
5.
Enable the Rx DMA (nothing will happen yet);
6.
Enable the Tx DMA (this starts both transfers);
7.
Wait for the Tx DMA transfer to complete;
8.
Wait for the Rx DMA transfer to complete (this will happen almost immediately);
9.
Deactivate Slave Select;
At the end of the transfer, the master and slave will have exchanged data.
