Application Note
AN_289 FT51A Programming Guide
Version 1.0
Document Reference No.: FT_000962 Clearance No.: FTDI# 483
14
Copyright © 2015 Future Technology Devices International Limited
2.2.2
SYSTEM_CLOCK_DIVIDER
Bit
Position Bit Field Name
Type Reset Description
7..5
RFU
R
0
Reserved
4
reset_8051
R/W
0
Set to reset the 8051 core.
This will cause the 8051
state and registers to be
reset. The program
counter will return to its
RESET value 0x0000. All
other modules and
peripherals except the top-
level registers will be
reset.
3
system_stop_request
R/W
0
For reduced power
consumption. When set
will stop all internal clocks
and place the chip in a low
power state.
Alternatively use PCON
SFR (more below).
2..1
clk_sys_divisor
R/W
0
1
0
Clock
division
0
0
1
0
1
2
1
0
4
1
1
8
0
hub_suspend_en
R/W
0
Allow the hub to enter
suspend mode.
Table 2.6 System and Clock Divider Register
Note:
When requesting a low power state and to obtain the lowest possible current
consumption the User must ensure all pad IO controls have no pull ups or downs enabled,
and are configured as an input. Also ensure that the external VCC3V3 is not under any
load conditions.
Note:
When running with clock division set to divide-by-8 certain functions are affected:
debugger access is NOT possible; UART cannot run at 3M BAUD. A minimum of divide-by-4
is advised for such operations.
Note:
Setting PCON SFR bit 0, so called Power Management Mode (PMM), reduces power
consumption by externally dividing the clock signal provided to the microcontroller,
causing it to operate at a reduced speed. When PMM is invoked, the external pin called
PMM is set into logic 1. It signalizes to external divider that CLK frequency should be
divided by 256. Note that all internal functions, on
‐
board timers (including serial port baud
rate generation), watchdog timer, and software timing loops will run at the reduced speed.
