Application Note
AN_289 FT51A Programming Guide
Version 1.0
Document Reference No.: FT_000962 Clearance No.: FTDI# 483
112
Copyright © 2015 Future Technology Devices International Limited
Comparator#
Programmed
Toggle Value
Pulse Width
(clock cycles)
0
7
1
8
1
2
12
3
14
2
4
15
5
16
1
6
19
7
22
3
Table 2.147 Programming 8 FT51A comparators to generate above waveform
For a simple duty cycle PWM, where only a single pulse is required, only 2 comparators would be
necessary and only a single pulse is generated. For example, to generate a 50% duty cycle
waveform for the clock/counter combination, comparators 0 & 1 could be programmed as follows:
Comparator#
Programmed
Toggle Value
Pulse Width
(clock cycles)
0
2
1
14
12
Table 2.148 Programming 2 FT51A comparators for 50 % duty cycle
In this example, there are 24 clocks per cycle and the PWM output changes state (toggles) every
12 clocks (12/24). This produces a 50 % duty cycle. By programming different toggling values into
the FT51A comparators, a wide range of duty cycles can be generated.
First parameter to decide on is the frequency of the PWM Clock. The highest possible PWM
frequency is 48MHz (no pre-scaling).
To derive the PWM Clock, set up the FT51A System Clock pre-scaler.
Pre-scale by 1 to get the PWM Clock equalling to a half of the FT51A System Clock.
Pre-scale by 255 to get the PWM Clock equalling to the FT51A System Clock divided by 256, etc.
Therefore to get the required PWM Clock frequency use the following formula and code:
PWM Clock = FT51A System Clock / (pr1)
//Set PWM prescaler to divide the FT51A System Clock by 2
WRITE_IO_REG(0x82, 0x01); //PWM_PRESCALER
To set the PWM sequence time, specify the number of PWM pulses to count from 0 to 65535:
PWM sequence period = (total PWM pulses) * (pr1)/ FT51A System Clock
,
where 0<= total PWM pulses <=65535.
And set the PWM counter value with the MSB and LSB registers as follows:
//Set PWM counter
WRITE_IO_REG(0x84, 0x12); //PWM_CNT16_MSB
WRITE_IO_REG(0x83, 0x34); //PWM_CNT16_LSB
