Application Note
AN_289 FT51A Programming Guide
Version 1.0
Document Reference No.: FT_000962 Clearance No.: FTDI# 483
30
Copyright © 2015 Future Technology Devices International Limited
2.3.6
SPI_MASTER_SETUP
Bit
Position
Bit Field Name
Type
Reset
Description
7..4
RFU
R
0
Reserved
3
spi_ss_n
R/W
1
SPI Slave Select. Used when the CPU
wishes to control a SS# signal. When
LOW is sets SS# active, when HIGH it
set it inactive.
2
lsbfirst
R/W
0
When HIGH, data is transferred LSB
first. When LOW, data is transferred
MSB first.
1
cpol
R/W
0
SPI Clock Polarity (CPOL) Bit - selects
the polarity of the SPI clk.
0
cpha
R/W
0
SPI Clock Phase (CPHA) Bit - selects
the phase of the SPI clk.
Table 2.28 SPI Master Setup Register
When transmitting data between SPI modules, both modules must be using the same CPOL and
CPHA values. A change to either of these bits aborts a transmission in progress and returns the
SPI system into an idle state.
Combined, the CPOL and CPHA settings make 4 modes that are listed in Table 8.
Mode 0 and 1: CPOL = 0, the base (inactive) level of SCLK is 0.
When CPHA = 0, data is clocked in on the rising edge of SCLK, and data is clocked out on the
falling edge of SCLK.
When CPHA = 1, data is clocked in on the falling edge of SCLK, and data is clocked out on the
rising edge of SCLK
Mode 2 and 3: CPOL =1, the base (inactive) level of SCLK is 1.
When CPHA = 0, data is clocked in on the falling edge of SCLK, and data is clocked out on the
rising edge of SCLK
When CPHA =1, data is clocked in on the rising edge of SCLK, and data is clocked out on the
falling edge of SCLK.
Mode
CPOL
CPHA
0
0
0
1
0
1
2
1
0
3
1
1
Table 2.29 SPI Master Mode Numbers
