Application Note
AN_289 FT51A Programming Guide
Version 1.0
Document Reference No.: FT_000962 Clearance No.: FTDI# 483
32
Copyright © 2015 Future Technology Devices International Limited
2.3.9
SPI_MASTER_SS_SETUP
Bit
Position
Bit Field Name
Type
Reset
Description
7..3
RFU
R
0
Reserved
2..1
ss_route
R/W
0
SPI Slave Select Route. Two bits set
the active slave select out of the 4
different slave selects.
0
ss_idle_state
R/W
1
SPI Slave Select Idle State.
Table 2.32 SPI Master Slave Select Setup
When setting the value of
ss_idle_state
: '1' sets an idle state of high, therefore SS# is active low;
'0' is an idle state of low, therefore SS# is active high.
2.3.10
SPI_MASTER_TRANSFER_SIZE
The SPI_MASTER_TRANSFER_SIZE register contains 16 bits and is split over 2 registers;
SPI_MASTER_TRANSFER_SIZE_L
at 0x69, and
SPI_MASTER_TRANSFER_SIZE_U
at 0x6A.
Bit
Position
Bit Field Name
Type
Reset
Description
7..0
xfer_size_l
R/W
0
Lower 8 bits of transfer size register.
Table 2.33 SPI Master Transfer Size (Lower) Register
Bit
Position
Bit Field Name
Type
Reset
Description
7..0
xfer_size_u
R/W
0
Upper 8 bits of transfer size register.
Table 2.34 SPI Master Transfer Size (Upper) Register
This allows the hardware to auto-control the assertion and de-assertion of slave select. Set the
lower byte first and then the upper byte. The
SPI_MASTER_DATA_DELAY
must be programmed with a
non-zero value when using these registers for automatic control over SS#.
Setting both bytes to 0 will abort a transfer in process.
If the transfer size is non-zero then the
spi_ss_n
bit in Section 0 should be set to ‘1’ (inactive).
