Application Note
AN_289 FT51A Programming Guide
Version 1.0
Document Reference No.: FT_000962 Clearance No.: FTDI# 483
123
Copyright © 2015 Future Technology Devices International Limited
FTDI Timer A
//Precautionary Top Level Soft Reset
WRITE_IO_REG(0x70, 0x01);
//TIMER_CONTROL, TIMER_SOFT_RESET
//Initialize timer by clearing it and the prescaler
WRITE_IO_REG(0x74, 0x11);
//TIMER_CONTROL_4, CLEAR_A | PRESC_CLEAR
//Top Level Enable
WRITE_IO_REG (0x70, 0x02);
//TIMER_CONTROL, TIMER_DEV_EN
//Select timer
WRITE_IO_REG (0x76, 0x00);
//TIMER_SELECT, TIMER A
//Write initial value
WRITE_IO_REG (0x79, 0xAA);
//TIMER_WRITE_MS
WRITE_IO_REG (0x78, 0xAA);
//TIMER_WRITE_LS
//Enable top-level interrupts
WRITE_IO_REG (0x05, 0x04
); //TOP_INT1_0, TIMER_IRQ
//Enable timer interrupt
WRITE_IO_REG (0x75, 0x02);
//TIMER_INT, TIMER_INT_A_IEN
//Set the prescaler
WRITE_IO_REG (0x72, 0x10);
//TIMER_CONTROL_2, PRESCALER_EN_0
//Start timer A
WRITE_IO_REG (0x71, 0x01);
//TIMER_CONTROL_1, START_A
FTDI Timers A, B, C and D require 1 cycle per instruction, whereas standard timers 0, 1 or 2
require either 12 (default) or 4 cycles per instruction. Additionally, the clock for Timers A, B, C and
D can also be pre-scaled, which changes the available time range. The maximum pre-scale value is
0xFFFF.
The delay range (in seconds) achievable with one 16-bit timer is shown in the table below. (Due to
the aforementioned 16-bit constraint, Timers 0 and 1 can only be in mode 1; timers A, B, C and D
can be in any mode.)
CLK
NUMBER OF CYCLES PER INSTRUCTION
12
4
1
48000000
0.00000025 - 0.01638375
8.33333E-08 - 0.00546125
2.08333E-08 - 0.001365313
24000000
0.0000005 - 0.0327675
1.66667E-07 - 0.0109225
4.16667E-08 - 0.002730625
12000000
0.000001 - 0.065535
3.33333E-07 - 0.021845
8.33333E-08 - 0.00546125
6000000
0.000002 - 0.13107
6.66667E-07 - 0.04369
1.66667E-07 - 0.0109225
Table 2.166 Available timer ranges (in seconds)
Yielding
MAX = 0.13107 s
MIN = 2.08333E-08 s
MAX-MIN = 0.131069979 s
