Application Note
AN_289 FT51A Programming Guide
Version 1.0
Document Reference No.: FT_000962 Clearance No.: FTDI# 483
31
Copyright © 2015 Future Technology Devices International Limited
The SPI Slave Select signal is enabled or disabled with the
spi_ss_n
bit. The
spi_ss_n
bit should
NOT be used in conjunction with SPI Transfer Size register.
Note:
When
spi_ss_n
is de-asserted the
cpol
bit should NOT be toggled at the same time.
Note:
The
lsbfirst
bit does not affect the order in which data is stored in the rx and tx
registers, simply the order in which data is transmitted and received.
2.3.7
SPI_MASTER_CLK_DIV
Bit
Position
Bit Field Name
Type
Reset
Description
7..0
clk_div
R/W
0
Clock divider register to determine
the frequency of the SPI clk signal.
Table 2.30 SPI Master Clock Divisor Register
The SPI Master clock can operate up to one half of the CPU system clock:
CPU running at 48Mhz would set the SPI maximum clock to 24Mhz
CPU running at 24Mhz would set the SPI maximum clock to 12Mhz
CPU running at 12Mhz would set the SPI maximum clock to 6hMz
The SPI Master clock frequency can be calculated:
Fsclk = (Fclk / 2) / div
Fsclk
- SPI Master clock frequency.
Fclk – CPU system clock frequency.
div – Clock divider.
If the CPU runs at 48MHz a divider value of both 0 and 1 will result in an SPI clock frequency of
24MHz.
2.3.8
SPI_MASTER_DATA_DELAY
Bit
Position
Bit Field Name
Type
Reset
Description
7..0
data_delay
R/W
0
Inserts a fixed delay between SS#
going active and the first SCLK cycle.
The value of this register is the
number of SCLK periods to delay.
For example, if SCLK is 100 kHz, a
value of 255 gives a delay of
2.55 ms.
Table 2.31 SPI Master Data Delay Register
It is recommended that this value is non-zero when using the Transfer Size feature for automatic
control over SS#.
