Application Note
AN_289 FT51A Programming Guide
Version 1.0
Document Reference No.: FT_000962 Clearance No.: FTDI# 483
20
Copyright © 2015 Future Technology Devices International Limited
Bit
Position
Bit Field Name
Type
Reset
Description
7
copy_mtp_2_ram
R/W
0
When set to 1 this shall copy the
contents of MTP block in to Shadow
RAM. The core is held in RESET and
code will start from address 0x0000
on completion of the copy.
The bit is cleared on completion of
the copy therefore the bit shall
always read as zero.
6
flash_mtp_mem
R/W
0
When set to 1 this shall copy the
contents of the Shadow RAM in to
MTP memory.
The bit is cleared on completion of
the copy.
5
mtp_byte_prog_done
R1C
0
Set when MTP BYTE write has
completed (See registers 0x2C,
0x2D, 0x2E). Cleared upon reading.
Note: This bit does NOT indicate
completion of a copy to MTP (see
bit 6)
4
mtp_mem_wr_failure
R
0
Set when a write fail occurs. A fail
can occur if the MTP byte write fails
to update to the new value within a
set programming time defined
internally.
3..0
RFU
R
0
Reserved
Table 2.13 MTP Control Register
When the
copy_mtp_2_ram
operation is performed it is advised to read the
mtp_byte_prog_done
register flag in
MTP_CONTROL
for completion. Then the status of the write can then be read from the
mtp_mem_wr_failure
bit.
2.2.10
MTP_ADDR_L, MTP_ADDR_U and MTP_PROG_DATA
Bit
Position
Bit Field Name
Type
Reset
Description
7..0
Data
R/W
0
Low byte of MTP Address
Table 2.14 MTP Address (Lower) Register
