Application Note
AN_289 FT51A Programming Guide
Version 1.0
Document Reference No.: FT_000962 Clearance No.: FTDI# 483
10
Copyright © 2015 Future Technology Devices International Limited
2.1
Hardware Access
The SFRs contain registers to allow direct access to the USB Full Speed device controller, I2C
Master and I2C Slave peripherals.
There are 10 sets of I/O ports that permit access to the registers of the ADC, PWM, SPI Master,
SPI Slave, UART FTDI, 245 FIFO, DMA, Timers, Watchdog and IOMUX.
Table 2.2 summarises the methods required to access each module.
Name
Method
Name
Method
ADC
I/O
GPIO FTDI
I/O
PWM
I/O
GPIO
SFR
SPI Master
I/O
AIO
SFR
SPI Slave
I/O
Debugger
SFR
I2C Master
SFR
Device Control
I/O
I2C Slave
SFR
IOMUX
I/O
UART FTDI
I/O
Timers 0, 1, 2
SFR
UART DCD
SFR
Timers A, B, C, D
I/O
245 FIFO
I/O
Watchdog FTDI
I/O
DMA Controller
I/O
Watchdog 8051
SFR
USB Device Hub Port
SFR
Table 2.2 FT51A Peripherals
2.1.1
Registers Accessed by SFR
For peripherals and modules addressed directly through the SFRs, the SDCC compiler provides a
“__sfr” keyword to allow their registers to be used like variables. For example, specify
__sfr __at (0x80) P0;
to allow access to port 0 via P0 variable. Refer to the
2.1.2
Registers Accessed through I/O Ports
To access a register via the I/O port method, the address of the register has to first be written to
one of the
IO_ADDR_x
SFRs; then the data can be read from, or written to, the matching
IO_DATA_x
SFR.
The I/O port address space is 9 bits, 0x000 to 0x1FF. Therefore the
IO_ADDR_x
SFRs have a high
and a low byte. The high byte is normally zero because only the IO Cell Controller is located above
the address 0xFF.
The SFRs contain 10 separate I/O ports. Writing to the address register for one port does not
interfere with an address written previously for a different port.
Example macros for writing and reading I/O ports are presented below:
