Freescale Semiconductor HCS08 Series, Reference Manual

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Chapter 3 Modes of Operation
MC9S08JS16 MCU Series Reference Manual, Rev. 4
Freescale Semiconductor 33
before writing to the PPDACK bit. If the port registers are not restored from RAM before writing to
PPDACK, then the pins will switch to their reset states when PPDACK is written.
For pins that are configured as peripheral I/O, the user must reconfigure the peripheral module that
interfaces to the pin before writing to the PPDACK bit. If the peripheral module is not enabled before
writing to PPDACK, the pins will be controlled by their associated port control registers when the I/O
latches are opened.
3.6.3 On-Chip Peripheral Modules in Stop Modes
When the MCU enters any stop mode, system clocks to the internal peripheral modules are stopped. Even
in the exception case (ENBDM = 1), where clocks to the background debug logic continue to operate,
clocks to the peripheral systems are halted to reduce power consumption. Refer to
Section 3.6.2, “Stop2
Mode ,” and Section 3.6.1, “Stop3 Mode ,” for specific information on system behavior in stop modes.
Table 3-2. Stop Mode Behavior
Peripheral
Mode
Stop2 Stop3
CPU Off Standby
RAM Standby Standby
Flash Off Standby
Parallel Port Registers Off Standby
MCG Off Optionally On
1
1
IREFSTEN set in MCGC1, else in standby.
RTC Optionally on
2
2
RTCPS[3:0] in RTCSC does not equal 0 before entering stop, else off.
Optionally on
2
SCI Off Standby
SPI Off Standby
MTIM Off Standby
TPM Off Standby
System Voltage Regulator Off Standby
XOSC Off Optionally On
3
3
EREFSTEN set in MCGC2, else in standby. For high frequency range (RANGE in
MCGC2 set), the LVD must also be enabled in stop3.
I/O Pins States Held States Held
USB (SIE and PHY) Off Optionally On
4
4
USBEN in CTL is set and USBPHYEN in USBCTL0 is set, else off.
USB 3.3 V Regulator Off Standby
USB RAM Standby Standby
CRC Off Standby