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16-Bit Serial Peripheral Interface (S08SPI16V1)
MC9S08JS16 MCU Series Reference Manual, Rev. 4
Freescale Semiconductor
191
13.1.4.1
SPI System Block Diagram
shows the SPI modules of two MCUs connected in a master-slave arrangement. The master
device initiates all SPI data transfers. During a transfer, the master shifts data out (on the MOSI pin) to the
slave while simultaneously shifting data in (on the MISO pin) from the slave. The transfer effectively
exchanges the data that was in the SPI shift registers of the two SPI systems. The SPSCK signal is a clock
output from the master and an input to the slave. The slave device must be selected by a low level on the
slave select input (SS pin). In this system, the master device has configured its SS pin as an optional slave
select output.
Figure 13-3. SPI System Connections
13.1.4.2
SPI Module Block Diagram
is a block diagram of the SPI module. The central element of the SPI is the SPI shift register.
Data is written to the double-buffered transmitter (write to SPIDH:SPIDL) and gets transferred to the SPI
shift register at the start of a data transfer. After shifting in 8 or 16 bits (as determined by SPIMODE bit)
of data, the data is transferred into the double-buffered receiver where it can be read (read from
SPIDH:SPIDL). Pin multiplexing logic controls connections between MCU pins and the SPI module.
When the SPI is configured as a master, the clock output is routed to the SPSCK pin, the shifter output is
routed to MOSI, and the shifter input is routed from the MISO pin.
When the SPI is configured as a slave, the SPSCK pin is routed to the clock input of the SPI, the shifter
output is routed to MISO, and the shifter input is routed from the MOSI pin.
In the external SPI system, simply connect all SPSCK pins to each other, all MISO pins together, and all
MOSI pins together. Peripheral devices often use slightly different names for these pins.
SPI SHIFTER
CLOCK
GENERATOR
SPI SHIFTER
SS
SPSCK
MISO
MOSI
SS
SPSCK
MISO
MOSI
MASTER
SLAVE
8 OR 16 BITS
8 OR 16 BITS
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