Freescale Semiconductor HCS08 Series, Reference Manual

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Cyclic Redundancy Check Generator (S08CRCV2)
MC9S08JS16 MCU Series Reference Manual, Rev. 4
Freescale Semiconductor 279
NOTE
Offsets 4, 5, 6 and 7 are also mapped onto the CRCL register. This is an alias
only used on CF1Core (version 1 of ColdFire core) and should be ignored
for HCS08 cores. See
Section 16.5, “Initialization Information” for more
details.
16.3.2 Register Descriptions
The CRC module includes:
• A 16-bit CRC result and seed register (CRCH:CRCL)
Refer to the direct-page register summary in the Chapter 4, “Memory ,” for the absolute address
assignments for all CRC registers. This section refers to registers only by their names. A
Freescale-provided equate or header file is used to translate these names into the appropriate absolute
addresses.
16.3.2.1 CRC High Register (CRCH)
16.3.2.2 CRC Low Register (CRCL)
7 6 5 4 3 2 1 0
R
Bit 15 Bit 14 Bit 13 Bit 12 Bit 11 Bit 10 Bit 9 Bit 8
W
Reset 0 0 0 0 0 0 0 0
Figure 16-3. CRC High Register (CRCH)
Table 16-2. Register Field Descriptions
Field Description
7:0
CRCH
CRCH — This is the high byte of the 16-bit CRC register. A write to CRCH will load the high byte of the initial 16-bit
seed value directly into bits 15-8 of the shift register in the CRC generator. The CRC generator will then expect the
low byte of the seed value to be written to CRCL and loaded directly into bits 7-0 of the shift register. Once both seed
bytes written to CRCH:CRCL have been loaded into the CRC generator, and a byte of data has been written to
CRCL, the shift register will begin shifting. A read of CRCH will read bits 15-8 of the current CRC calculation result
directly out of the shift register in the CRC generator.
7 6 5 4 3 2 1 0
R
Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
W
Reset 0 0 0 0 0 0 0 0
Figure 16-4. CRC Low Register (CRCL)