Freescale Semiconductor HCS08 Series, Reference Manual

Page: 74 / 306

Chapter 5 Resets, Interrupts, and System Configuration
MC9S08JS16 MCU Series Reference Manual, Rev. 4
74 Freescale Semiconductor
5.7.5 System Options Register 2 (SOPT2)
1
BKGDPE
Background Debug Mode Pin Enable — This write-once bit when set enables the PTB2/BKGD/MS pin to
function as BKGD/MS. When clear, the pin functions as one of its output-only alternative functions. This pin
defaults to the BKGD/MS function following any MCU reset.
0 PTB2/BKGD/MS pin functions as PTB2.
1 PTB2/BKGD/MS pin functions as BKGD/MS.
0
RSTPE
RESET Pin Enable — This write-once bit when set enables the PTB1/RESET pin to function as RESET. When
clear, the pin functions as one of its alternative functions. This pin defaults to a general-purpose input port
function following a POR reset. When configured as RESET, the pin will be unaffected by LVR or other internal
resets. When RSTPE is set, an internal pullup device is enabled on RESET.
0 PTB1/RESET pin functions as PTB1.
1 PTB1/RESET pin functions as RESET.
Table 5-6. COP Configuration Options
Control Bits
Clock Source
COP Window
1
Opens
(COPW = 1)
1
Windowed COP operation requires the user to clear the COP timer in the last 25% of the selected timeout period. This column
displays the minimum number of clock counts required before the COP timer can be reset when in windowed COP mode
(COPW = 1).
COP Overflow Count
COPCLKS COPT[1:0]
N/A 0:0 N/A N/A COP is disabled
0 0:1
1 kHz N/A
2
5
cycles (32 ms
2
)
2
Values shown in milliseconds based on t
LPO
= 1 ms. See t
LPO
in the MC9S08JS16 Data Sheet for the tolerance of this value.
0 1:0
1 kHz N/A
2
8
cycles (256 ms
2
0 1:1
1 kHz N/A
2
10
cycles (1.024 s
2
)
1 0:1
Bus 6144 cycles
2
13
cycles
1 1:0
Bus 49,152 cycles
2
16
cycles
1 1:1
Bus 196,608 cycles
2
18
cycles
7 6 5 4 3 2 1 0
R
COPCLKS
1
COPW
1
0 0 0
SPIFE
0 0
W
Reset 0 0 0 0 0 1 0 0
= Unimplemented or Reserved
1
This bit can be written only one time after reset. Additional writes are ignored.
Figure 5-6. System Options Register 2 (SOPT2)
Table 5-5. SOPT1 Register Field Descriptions (continued)
Field Description