Freescale Semiconductor HCS08 Series, Reference Manual

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16-Bit Serial Peripheral Interface (S08SPI16V1)
MC9S08JS16 MCU Series Reference Manual, Rev. 4
190 Freescale Semiconductor
13.1.2 Features
The SPI includes these distinctive features:
• Master mode or slave mode operation
• Full-duplex or single-wire bidirectional mode
• Programmable transmit bit rate
• Double-buffered transmit and receive data register
• Serial clock phase and polarity options
• Slave select output
• Mode fault error flag with CPU interrupt capability
• Control of SPI operation during wait mode
• Selectable MSB-first or LSB-first shifting
• Programmable 8- or 16-bit data transmission length
• Receive data buffer hardware match feature
13.1.3 Modes of Operation
The SPI functions in three modes, run, wait, and stop.
• Run Mode
This is the basic mode of operation.
• Wait Mode
SPI operation in wait mode is a configurable low power mode, controlled by the SPISWAI bit
located in the SPIC2 register. In wait mode, if the SPISWAI bit is clear, the SPI operates like in
Run Mode. If the SPISWAI bit is set, the SPI goes into a power conservative state, with the SPI
clock generation turned off. If the SPI is configured as a master, any transmission in progress stops,
but is resumed after CPU goes into Run Mode. If the SPI is configured as a slave, reception and
transmission of a byte continues, so that the slave stays synchronized to the master.
• Stop Mode
The SPI is inactive in stop3 mode for reduced power consumption. If the SPI is configured as a
master, any transmission in progress stops, but is resumed after the CPU goes into Run Mode. If
the SPI is configured as a slave, reception and transmission of a data continues, so that the slave
stays synchronized to the master.
The SPI is completely disabled in all other stop modes. When the CPU wakes from these stop modes, all
SPI register content will be reset.
This is a high level description only, detailed descriptions of operating modes are contained in section
Section 13.4.9, “Low Power Mode Options .”
13.1.4 Block Diagrams
This section includes block diagrams showing SPI system connections, the internal organization of the SPI
module, and the SPI clock dividers that control the master mode bit rate.