Freescale Semiconductor HCS08 Series, Reference Manual

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16-Bit Serial Peripheral Interface (S08SPI16V1)
MC9S08JS16 MCU Series Reference Manual, Rev. 4
202 Freescale Semiconductor
If the CPHA bit is set, even numbered edges on the SPSCK input cause the data at the serial data input pin
to be latched. Odd numbered edges cause the value previously latched from the serial data input pin to shift
into the LSB or MSB of the SPI shift register, depending on the LSBFE bit.
When CPHA is set, the first edge is used to get the first data bit onto the serial data output pin. When CPHA
is clear and the SS input is low (slave selected), the first bit of the SPI data is driven out of the serial data
output pin. After the eighth (SPIMODE = 0) or sixteenth (SPIMODE = 1) shift, the transfer is considered
complete and the received data is transferred into the SPI data registers. To indicate transfer is complete,
the SPRF flag in the SPI Status Register is set.
NOTE
A change of the bits CPOL, CPHA, SSOE, LSBFE, MODFEN, SPC0 and
BIDIROE with SPC0 set and SPIMODE in slave mode will corrupt a
transmission in progress and has to be avoided.
13.4.4 Data Transmission Length
The SPI can support data lengths of 8 or 16 bits. The length can be configured with the SPIMODE bit in
the SPIC2 register.
In 8-bit mode (SPIMODE = 0), the SPI Data Register is comprised of one byte: SPIDL. The SPI Match
Register is also comprised of only one byte: SPIML. Reads of SPIDH and SPIMH will return zero. Writes
to SPIDH and SPIMH will be ignored.
In 16-bit mode (SPIMODE = 1), the SPI Data Register is comprised of two bytes: SPIDH and SPIDL.
Reading either byte (SPIDH or SPIDL) latches the contents of both bytes into a buffer where they remain
latched until the other byte is read. Writing to either byte (SPIDH or SPIDL) latches the value into a buffer.
When both bytes have been written, they are transferred as a coherent 16-bit value into the transmit data
buffer.
In 16-bit mode, the SPI Match Register is also comprised of two bytes: SPIMH and SPIML. Reading either
byte (SPIMH or SPIML) latches the contents of both bytes into a buffer where they remain latched until
the other byte is read. Writing to either byte (SPIMH or SPIML) latches the value into a buffer. When both
bytes have been written, they are transferred as a coherent 16-bit value into the transmit data buffer.
Any switching between 8- and 16-bit data transmission length (controlled by SPIMODE bit) in master
mode will abort a transmission in progress, force the SPI system into idle state, and reset all status bits in
the SPIS register. To initiate a transfer after writing to SPIMODE, the SPIS register must be read with
SPTEF = 1, and data must be written to SPIDH:SPIDL in 16-bit mode (SPIMODE = 1) or SPIDL in 8-bit
mode (SPIMODE = 0).
In slave mode, user software must write to SPIMODE only once to prevent corrupting a transmission in
progress.
NOTE
Data can be lost if the data length is not the same for both master and slave
devices.