Freescale Semiconductor HCS08 Series, Reference Manual

Page: 80 / 306

Chapter 6 Parallel Input/Output
MC9S08JS16 MCU Series Reference Manual, Rev. 4
80 Freescale Semiconductor
Figure 6-1. Parallel I/O Block Diagram
The data direction control bits determine whether the pin output driver is enabled. Each port pin has a data
direction register bit. When PTxDDn = 0, the corresponding pin is an input and reads of PTxD return the
pin value. When PTxDDn = 1, the corresponding pin is an output and reads of PTxD return the last value
written to the port data register. When a peripheral module or system function is in control of a port pin,
the data direction register bit still controls what is returned for reads of the port data register, even though
the peripheral system has overriding control of the actual pin direction.
When a shared analog function is enabled for a pin, all digital pin functions are disabled. A read of the port
data register returns a value of 0 for any bit which has shared analog functions enabled. In general,
whenever a pin is shared with both an alternate digital function and an analog function, the analog function
has priority such that if both the digital and analog functions are enabled, the analog function controls the
pin.
Write to the port data register before changing the direction of a port pin to output. This ensures that the
pin will not be driven momentarily with an old data value that happened to be in the port data register.
6.3 Pin Control
The pin control registers are located in the high-page register block of the memory. These registers are used
to control pullups, slew rate, and drive strength for the I/O pins. The pin control registers operate
independently of the parallel I/O registers.
Q D
Q D
1
0
Port Read
PTxDDn
PTxDn
Output Enable
Output Data
Input Data
Synchronizer
Data
BUSCLK